Aha! That makes sense

Simulated artificial mouth??????

GLUE watches a bit 1: when it is "0" then VBL is 50Hz (or 60Hz) and HBL is 15kHz; when it is "1" then VBL is 72Hz and HBL is 32kHz. SHIFTER watches bits 0 and 1: when they are "01" then pixelock is 16MHz and color mode MID when they are "00" then pixelock is 8MHz and color mode LOW when bit 1 is se...

Heh, well, it was an idea

I use some wires that I have attached to the 68901 IO controller, hanging out the side. Best current option is to plug in a board to the monitor socket and switch the pin to ground that way (but those DIN-14 plugs are expensive). Ultimately that pin in the monitor socket is just a piece of informati...

I have a question Petari,

You know the Desktop -> Preferences dialog, where you switch between "Low" and "Medium" resolutions - is there any chance to have all three resolutions enabled at all times so that people who use a 50/71Hz-compatible monitor can access all the modes?

I love the bee logo! Very nice

As said, I'm not good with C. So, you mean that should change something at ASM parts syntax ? Or you mean that not use 68000 ASM at all ? I don't think that it can be done without serious speed problems and lot of time. Early stage - HW init, test, BIOS is done in ASM. Then interrupt handlers, beca...

If you're going to update the TOS code to make it compatible with modern C compilers, I would like to suggest that you break with the tradition of using the obsolete assembler syntax that necessitates the use of gcc-68k-atari-mint. Standard gcc syntax is way more portable. If you have to build a cus...

Yeah if you have cycle accuracy detection of DE and LOAD then you can. The cause of the pixel offset is that the wakestates have different DE-to-LOAD delays. 3,4,5 and 6 cycles respectively for WS2, WS4, WS3 and WS1. I experimented with this and found a correlation. Measuring the latency from DE to...