Atarian Computing wrote: ↑Sun Mar 10, 2019 9:03 am The logo image is 96px wide and I assumed 96px high but my first attempt was cropped. So not sure of exact height.

Height is 86 pixels.
Bigger logos are also possible. I remember I was using a logo more than 96 pixels wide.. long time ago..

PM

Hm.. l will see..
Meanwhile let's try a hack: Insert GAL U6 in a way that pin17 goes outside the socket (no connection between pin17 and the PAK). Try to boot, and run GemBench with D&I cache on..

Do you have a spare GAL available?
Use that to swap it with U6 which is currently in use.

Sorry, I was wrong..
Please check U6 14 to pin 52.
(Should be 0 Ohm as well)

Ok, good news: The L1 cache works, but only in the ROM area. Let's look further..
Please confirm 2 connections:
1. From U6 pin 11 to 68000 connector pin 51 (A22)
2. From U6 pin 13 to 68000 connector pin 52 (A23)

Another test:
Please set J2 = J3 = J4 = off.
Run GemBench twice:
1. With I & D cache both enabled
2. With I & D cache both disabled
and post the screenshots.

Measure the resistance from U6 pin17 to VCC and GND

Measure the resistance from U2 pin1 to U1 pin11 to J11 pin2 to J11 pin1 to the CPU pin C02. All should be connected.

Measure the resistance from U1 pin11 to GND and VCC