Search found 90 matches

by ijor
Sun Jun 09, 2019 2:26 pm
Forum: MEMBER BLOGS
Topic: exxos blog - random goings on
Replies: 532
Views: 39265

Re: exxos blog - random goings on

I was looking at the ste combo schematic and found the clock dividers. Interestingly the reset lines are all tied ultimately to a test pin. I assume its there to allow the debug guys to start the machine from a known state each time. Doesn't help with the ST MMU, but just thought I would look anywa...
by ijor
Fri Jun 07, 2019 8:12 pm
Forum: MEMBER BLOGS
Topic: exxos blog - random goings on
Replies: 532
Views: 39265

Re: exxos blog - random goings on

I did try using the MMU 8Mhz (now 16MHz) and running that into the 161 to generate the clocks, but still had random start up issues as before. So I don't think its totally down to wake up states on the MMU causing issues. If the MMU had a reset pin there wouldn't be any issues (or at least a lot le...
by ijor
Fri Jun 07, 2019 5:12 pm
Forum: MEMBER BLOGS
Topic: exxos blog - random goings on
Replies: 532
Views: 39265

Re: exxos blog - random goings on

So the only way forward is to continue with the FPGA stuff. if we develop a FPGA board to fit the current remake board, to replace the MMU & GLUE for starters ( I do not know if this will be better all inside a single FPGA or combine the 2 cores into a single FPGA chip) , but in anycase, could you ...
by ijor
Fri Jun 07, 2019 4:28 pm
Forum: MEMBER BLOGS
Topic: exxos blog - random goings on
Replies: 532
Views: 39265

Re: exxos blog - random goings on

I am assuming that there are some internal FF's in the MMU doing the clock divisions which start up at the random state, I know there are "wake up states" relating to the shifter etc but this is a PITA now :( Correct. There are clock divisions at SHIFTER, MMU & GLUE, and all of them involve wake st...
by ijor
Thu Jun 06, 2019 2:53 pm
Forum: MONGREL EDITION DEVELOPMENT & INFO
Topic: Clocking
Replies: 6
Views: 653

Re: Clocking

I've read that thread where Troed discussed the issue, and I don't agree with him 100%. IMHO very few demos would be affected. But yes, it is not very good to have a squared 8 MHz frequency. I was mostly thinking in loud voice. This would probably become more critical when (and if) the frequency is ...
by ijor
Thu Jun 06, 2019 2:23 pm
Forum: MONGREL EDITION DEVELOPMENT & INFO
Topic: Clocking
Replies: 6
Views: 653

Re: Clocking

I see. A few comments. Using a sync counter like that is not the best way to avoid clock skew. You still has the Tco (clock to ouput) delay from 32 MHz. That is equivalent to a clock division and will produce a significant skew. Although it certainly won't be as bad as the chain of divisions that th...
by ijor
Wed Jun 05, 2019 8:05 pm
Forum: MONGREL EDITION DEVELOPMENT & INFO
Topic: Clocking
Replies: 6
Views: 653

Clocking

Quoting from a different subforum, but probably better to follow up here: In terms of clock distribution and division, on the remake board, we simply just used a LS161 synchronous binary counter. So we can feed in 32MHz and get 16,8,4,2 MHz output all in phase. I can't see this in the H1 schematics,...
by ijor
Sun Jun 02, 2019 7:32 pm
Forum: MONGREL EDITION DEVELOPMENT & INFO
Topic: True 16MHz Mode
Replies: 111
Views: 10701

Re: True 16MHz Mode

Yeah, Troed did a table of all this somewhere in his tread. Of course it needs the bandwidth to RAM to output the data fast enough, but also needs a shifter capable of using the bandwidth. ... So we basically go from 320x200x16 to 640x200x16 which is double bandwidth needed. So 640x200x16 would nee...
by ijor
Sat May 18, 2019 10:33 pm
Forum: ALPHA DEVELOPMENT INFO
Topic: STE DAC FPGA issues
Replies: 16
Views: 2125

Re: STE DAC FPGA issues

That can be done with switches or even controlled via a register. A software switch is not good enough, it is not foolproof. Anything that can be controlled via software is yet another potential incompatibility. At least unless the switch is one way only . If you can enable "full compatible mode" v...
by ijor
Sat May 18, 2019 10:19 pm
Forum: ALPHA DEVELOPMENT INFO
Topic: STE DAC FPGA issues
Replies: 16
Views: 2125

Re: STE DAC FPGA issues

Initially we are testing each core one by one starting with the blitter. Once all cores are tested as working how we want (IE 100% compatible) then those cores will be integrated into a single FPGA. The STE was basically the same, as in integrating GLUE,SHIFTER,MMU "all in one chip" so doing the sa...

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