You have ROM_OE on pin 29

I don't see the SRAM[1..4] signals on the CPLD

This is all very interesting. On our 68020board I did put 100nF on all power pins as close as possible to them (1206 packages). This does make things harder to route (both for me and the auto router). I might have to reconsider the number of caps and their placement to lower the count and do a you d...

I used both a Logic 8 and a Logic Pro 16 from Saleae. I did test a bunch of cheap ones (up to 32 channel like exxos, we had the same one) just to see them fail miserably and not work as expected. I think buying the Saleae Logic Pro 16 was the best thing I did to help me debug the 68020 board. If you...

Yep, with CDIS jumpered if it still fails it obviously not a cache issue. The floppy uses the DMA so may be a BR/BG/BGACK issue with retaking the bus to quickly with DMA data lingering on the bus. On our 68020 board we resync these (I assume you do the same) to the 8MHz clock. If I think of somethin...

IT's probably a cache issue. You should only allow caching for the RAM, TOS and eventually fastRam (AltRam). This is the VHDL from the test we did on the 68020 board when we put a 68030 on it (via a small adapter) : -- 68030 experimentation CIIN <= '1' when (Address_bus >= x"00E00000" and Address_bu...

This is great news.


Rodolphe

Once we have a stable version of the board and everything is open sourced we can almost drop it in on the schematics as it interfaces directly in place of the 68000. We also have an expansion port on the board too .. to be discussed when the time comes.

STF-Remake + 68030@50MHz + 32 bit TOS + sh*tload of AtlRam