You are a brave man. Hope it works out. In case you don't want to fiddle with that analog switch stuff, you might like my latest sketch. It has extra wires out for DA4/5 for the chips that don't need the bit reversed as well as the flipped one. I don't understand exactly this circuit. Is DA4_0 the ...

exxos wrote: ↑

Sun Nov 10, 2019 9:25 pm

plus what is inside each block...

We could reimplement the blitter using 74x series chips!!! It'll be HUGE!

AFAIK the Amiga blitter can combine 2 (or maybe even 3) sources into a single destination, the Atari blitter can only combine a single source with a single destination, overwriting the destination in the process. I'm sure it can be done though. actually Atari BLiTTER can combine three sources: 1) S...

I made a life using "grafics"-operations, but with the CPU. It's nicely fast and small (it fits in a boot sector). I got that idea from someone who did life with blitter on the Amiga. As you also found out, you only need to count to 4. It is a reimplementation of an adder logic chip by using logic ...

I will get myself a couple YMs and components and cobble together something to check if it works. You are a brave man. Hope it works out. In case you don't want to fiddle with that analog switch stuff, you might like my latest sketch. It has extra wires out for DA4/5 for the chips that don't need t...

The 68k sets bdir & bc1 & address %0001xxxx YM0 ignores this, as address is not 0000 YM1, because of delay on the D4 line, also sees 0001, so ignores. then D4 goes low (gets inverted by our additional circuitry) and YM1 sees 0000 and that's a valid address/bdir/bc1 combination, and so it latches th...

Sure its a FlipFlop, but why 2 clock inputs, They are just C and /C driven by a inverter elsewhere. Normally C would latch on the falling edge, and /C Would latch on the rising edge. But this one has both. I've noticed this funkyness all over with other blocks as well. I think only 1 clock is neede...

I'm assuming LDS UDS might need to be used to ensure there is valid data on the bus. It's not the original data, it's the delay caused by manipulating the data bits when writing the register number to the YM. Originally we know that when BDIR and BC1 are valid, the data bus is already valid (otherw...

With a bit of trying again and again (and making the tri-state gates ideally fast at 0ms) it seems to work sometimes. At least I managed to load into R1 of both YMs 2 different values. i.e. R1 = $19 and R17 = $11 Yes there is probably a timing issue. I think you will have to delay the BC1 and BDIR ...

Here's my latest attempt at doing this correctly. This version should be able to add 3 additional YM chips for a total of 12 audio channels! The first extra chip should replace it's DA4 pin connection with DA4_FLIPPED, the second should connect its DA5 pin to DA5_FLIPPED, and the third one should co...