Search found 17 matches

by slingshot
Thu Feb 27, 2020 12:35 pm
Forum: FPGA DEVELOPMENT
Topic: ST FPGA MMU Development
Replies: 46
Views: 21475

Re: ST FPGA MMU Development

If you want to run Closure, you need a cycle exact GLUE & MMU, and I think Suska is far from that. It's not just the wake state. Btw, my opinion is to have a good MMU first, with the original Glue, because the Glue chip which is responsible for the basic timing things (horizontal/vertical counte...
by slingshot
Thu Nov 14, 2019 1:14 pm
Forum: FPGA DEVELOPMENT
Topic: BLITTER RE-CREATION THOUGHTS
Replies: 423
Views: 189626

Re: BLITTER RE-CREATION THOUGHTS

4082 I believe is part of the STE combel or some other versions of it, so its of no use to use really. https://www.exxosforum.co.uk/forum/viewtopic.php?f=29&t=2302 Just asked because seems it uses a more modern ASIC library, just compare the first pages (which is the most important part - the s...
by slingshot
Thu Nov 14, 2019 1:01 pm
Forum: FPGA DEVELOPMENT
Topic: BLITTER RE-CREATION THOUGHTS
Replies: 423
Views: 189626

Re: BLITTER RE-CREATION THOUGHTS

I've started to look at the schematics more thoughtfully. Anybody has an idea if a Blitter interrupt is generated when it's restarted in non-hog mode? It should because of how the busy bit implemented: it's cleared when the operation finishes _and_ when the register containing the busy bit is select...
by slingshot
Thu Nov 14, 2019 11:59 am
Forum: FPGA DEVELOPMENT
Topic: BLITTER RE-CREATION THOUGHTS
Replies: 423
Views: 189626

Re: BLITTER RE-CREATION THOUGHTS

Nice! Not sure if Icky mentioned, though he sort-of had it running last night... got a bit more in speed, but still 42% which is still running half speed basically than it should. Good, it could be integrated then. The speed problem is basically the state machine have some extra states besides the ...
by slingshot
Thu Nov 14, 2019 9:14 am
Forum: FPGA DEVELOPMENT
Topic: BLITTER RE-CREATION THOUGHTS
Replies: 423
Views: 189626

Re: BLITTER RE-CREATION THOUGHTS

Meanwhile I found the issue why the blitter from Suska is slow, and even fixed the FC output from user to supervisor data (that allows write to the Shifter palette registers). Hell, it runs some demos now (like 20 years megademo, the Happy Birthday scene)! Just need a bit more work on the state mach...
by slingshot
Wed Nov 13, 2019 12:27 pm
Forum: FPGA DEVELOPMENT
Topic: BLITTER RE-CREATION THOUGHTS
Replies: 423
Views: 189626

Re: BLITTER RE-CREATION THOUGHTS

Cyprian wrote: Wed Nov 13, 2019 11:41 am
I spent so many hours to find a bug in my blitter code, which finally appeared that CPU access counting.
I will change the code to count AS edges instead of pure clock ticks. Maybe it'll fix everything magically :) (Well, don't think so, but probably will better).
by slingshot
Wed Nov 13, 2019 10:40 am
Forum: FPGA DEVELOPMENT
Topic: BLITTER RE-CREATION THOUGHTS
Replies: 423
Views: 189626

Re: BLITTER RE-CREATION THOUGHTS

If I'm not wrong, in the Suska's code I see that wrong 64/64 split scheme, and also I can't see code responsible for counting cycles used by the CPU. On the schematics, it can be seen that the HOG counter counts the XASI signal (incoming AS when the CPU is the bus master, outgoing when the Blitter ...
by slingshot
Tue Nov 12, 2019 9:56 pm
Forum: FPGA DEVELOPMENT
Topic: BLITTER RE-CREATION THOUGHTS
Replies: 423
Views: 189626

Re: BLITTER RE-CREATION THOUGHTS

Just trying to figure out how to sort out the CLK_EN_p and CLK_EN_n what with that and the distraction of almost getting my printer to do a first ever print this evening :) Here's an example in ijor's FX68K how to create the two clock enables (it's for 32MHz, so divides by 4, but easy to convert to...
by slingshot
Tue Nov 12, 2019 9:52 pm
Forum: FPGA DEVELOPMENT
Topic: BLITTER RE-CREATION THOUGHTS
Replies: 423
Views: 189626

Re: BLITTER RE-CREATION THOUGHTS

"Release the bus for 64 CLK cycles." - it uses wrong cycle split scheme I've also changed that back to 64/64. I don't know how the original performs, but my main interest is demo compatibility, which require cycle perfect operation, and it's hard to achieve without having this as a design...
by slingshot
Tue Nov 12, 2019 8:25 pm
Forum: FPGA DEVELOPMENT
Topic: BLITTER RE-CREATION THOUGHTS
Replies: 423
Views: 189626

Re: BLITTER RE-CREATION THOUGHTS

I've succesfully integrated the Suska's blitter in the MiST core. Added a small patch, which fixed the clocking: https://github.com/gyurco/MiSTery/commit/e43ff9460e2c4a133834f4c713e5446f252776f7 Basically converted to a two-phase clock-enable structure, that means you need at least 16MHz clock for a...

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