I think we need to get you setup with some verilog test benches so you can verify your code in a sim.

Todd wrote: ↑

Fri Mar 05, 2021 6:55 am

Without sounding stupid, is it possible to buy a TF1260 .. ?

Nope.

assign rom_decode2 = ({A[31:16]} != {16'h00E}); Is this right to decode [E00000..EFFFFF] ? Saying that I had to remove 2 upper address lines to break out the ROM decode wires... hmm.. No... h00E is 12 bits. left and right hand side need to match and verilog compilers are not the best at warning... ...

Recommend this site for small snips

http://www.asic-world.com/verilog/veritut.html

exxos wrote: ↑

Thu Mar 04, 2021 1:12 pm

@terriblefire Do counters count to the max count (111 in my case) then stop or cycle back to 000 ?

They keep rolling over.

If I do reg wire rom_decode2; ERROR:HDLCompilers:26 - "rtl/main_top.v" line 286 unexpected token: 'wire' ERROR:HDLCompilers:26 - "rtl/main_top.v" line 286 unexpected token: ';' If I do reg rom_decode2; ERROR:HDLCompilers:246 - "rtl/main_top.v" line 289 Reference to scalar reg 'rom_decode2' is not a...

So after 4 hours I give up, I don't get verilog at all.. my current code is.. reg rom_access; wire rom_decode; reg [3:0] qc; wire rom_decode2; wire [15:0] rom_dout; assign rom_decode2 = ({A[31:16]} != {16'h00E}); //assign rom_decode = 1'b1; //assign rom_decode = 0'b0; // A synchronous clear counter...

A good rule for rocket experimenters to follow is this: always assume that it will explode.

— Astronautics, issue 38, October 1937.

kludge wrote: ↑

Wed Mar 03, 2021 4:10 pm

So... What do we have here?


A75B423F-FB95-4DB9-8463-98BA38C44F6B.jpeg

Swedish clones!

The TF530 behaves much better with the FPU in ...

DiagROM do anything?