Wow, looks awesome. That must have involved some layout voodoo?

I read somewhere that he was born in 1966... so about 53 or 54 years old.
Very tragic indeed! RIP, Curt!

It's so... so... pink!

Icky wrote: ↑

Tue Jul 28, 2020 9:10 pm

A bit of manipulation and we now have a slot-in rear panel allowing different panel layouts.

Slick! That's pretty awesome!

exxos wrote: ↑

Fri Jan 24, 2020 1:49 pm

I think I now have the worlds supply of DB19F connectors

Holy moly! How many did you buy? 1000? From where?

On the schematics, it can be seen that the HOG counter counts the XASI signal (incoming AS when the CPU is the bus master, outgoing when the Blitter is), that's how many times the CPU/Blitter accesses the memory. Yeah, it's not implemented this way in Suska. I spent so many hours to find a bug in m...

Icky wrote: ↑

Tue Oct 15, 2019 11:15 am

Just thought I would share some videos of the FPGA Blitter Board running using the stock code at different clock speeds and the effects it has.

Running @ 8MHz
...
Running @ 16MHz
...
Running @ 32MHz
...

What about 64MHz?

I have been mulling the Nova fit within the TT and MegaSTE for sometime now and the Nova VME board with the ISA board is quite a lot of overkill in space. I have a side project idea on the go to recreate the Nova VME and ISA board as one inside the TT / Mega STE with the metal shielding removed so ...

Wow! That's quite an achievement! Congratulations!

Wietze, I forced the i-cache off in our JOY demo and it then behaves exactly like the video you sent me of your computer running it. The problems starts on the same frame, so it seems like your i-cache is disabled (by hardware) or malfunctioning. It's not due to software control as in the released v...