On the schematics, it can be seen that the HOG counter counts the XASI signal (incoming AS when the CPU is the bus master, outgoing when the Blitter is), that's how many times the CPU/Blitter accesses the memory. Yeah, it's not implemented this way in Suska. I spent so many hours to find a bug in m...

Icky wrote: ↑

Tue Oct 15, 2019 11:15 am

Just thought I would share some videos of the FPGA Blitter Board running using the stock code at different clock speeds and the effects it has.

Running @ 8MHz
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Running @ 16MHz
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Running @ 32MHz
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What about 64MHz?

I have been mulling the Nova fit within the TT and MegaSTE for sometime now and the Nova VME board with the ISA board is quite a lot of overkill in space. I have a side project idea on the go to recreate the Nova VME and ISA board as one inside the TT / Mega STE with the metal shielding removed so ...

Wow! That's quite an achievement! Congratulations!

Wietze, I forced the i-cache off in our JOY demo and it then behaves exactly like the video you sent me of your computer running it. The problems starts on the same frame, so it seems like your i-cache is disabled (by hardware) or malfunctioning. It's not due to software control as in the released v...

The TT is a fairly rare machine and should sell for at least 400 GBP if in good working condition.

rpineau wrote: ↑

Thu Mar 28, 2019 2:07 pm

MemoryX has EDO 60ns non parity : https://www.memoryx.com/32mbx326e.html

Those seem to need a 4k refresh which I've been told is not supported by the Storm card.

One more fun thing left to do. Take the "screws" out on the DSUB-19 connector and loosely fit them the the other way around, otherwise you won't be able to plug them into the Falcon's monitor port. Yeah, it sucks I know!

Congratulations! This is pretty awesome! Impressive work!

Seems like an amazing conversion with extensive support for various accelerators! Impressive work!