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by Smonson
Fri Nov 03, 2017 6:12 am
Forum: FPGA DEVELOPMENT
Topic: Project: HDMI/DVI out for STFM
Replies: 610
Views: 122024

Project: HDMI/DVI out for STFM

Data lines (and address lines) should be pulled up on 68K systems, not down. So I'll say the first step is to fix the pull-down to be pull-up. I don't think there's any difference in this case, the shifter's bus isn't connected to the 68K. As long as it's not oscillating between two logic states, i...
by Smonson
Fri Nov 03, 2017 1:22 am
Forum: FPGA DEVELOPMENT
Topic: Project: HDMI/DVI out for STFM
Replies: 610
Views: 122024

Project: HDMI/DVI out for STFM

Both, but I have made an assumption that RW is LOW for a register read - when I should be driving the shifter bus - and HIGH for a write. But I have no real way to confirm. I would assume it would follow the CPU RW states as the CPU program the registers ? Sorry, I had it around the wrong way. High...
by Smonson
Thu Nov 02, 2017 12:26 pm
Forum: FPGA DEVELOPMENT
Topic: Project: HDMI/DVI out for STFM
Replies: 610
Views: 122024

Project: HDMI/DVI out for STFM

Is it doing a read or write though ? Both, but I have made an assumption that RW is LOW for a register read - when I should be driving the shifter bus - and HIGH for a write. But I have no real way to confirm. Another assumption (I seem to be making a lot of these lately) is that the shifter needs ...
by Smonson
Thu Nov 02, 2017 12:12 am
Forum: FPGA DEVELOPMENT
Topic: Project: HDMI/DVI out for STFM
Replies: 610
Views: 122024

Project: HDMI/DVI out for STFM

Since you mention 50Hz, I'm assuming you're dealing with PAL frequencies. A PAL frame supposedly consists of 625 scan lines (visible and invisible lines) transmitted as two 50Hz interlaced fields. The Atari image, being progressive basically treats each field as a separate frame, but note how the n...
by Smonson
Thu Nov 02, 2017 12:00 am
Forum: FPGA DEVELOPMENT
Topic: Project: HDMI/DVI out for STFM
Replies: 610
Views: 122024

Project: HDMI/DVI out for STFM

TOS boot process can be seen in the disassembly in ST Internals, if not in the actual TOS source available. It writes to video mode registers of course, but I'm not sure it reads. Maybe some HBL interrupts etc could be affected. In any case, booting from a diagnostic cartridge is often a good way t...
by Smonson
Wed Nov 01, 2017 11:54 pm
Forum: FPGA DEVELOPMENT
Topic: Project: HDMI/DVI out for STFM
Replies: 610
Views: 122024

Project: HDMI/DVI out for STFM

Update: got my boards from the fabricator. Nice stuff :) I assume the green boards are the ones you created, and the blue one is a off-the-shelf cyclone board? If so I should probably get myself one of these boards the development work.. That's right. They're known as "EP2C5 Mini-Boards" on ebay. T...
by Smonson
Wed Nov 01, 2017 11:36 pm
Forum: HARDWARE DISCUSSIONS
Topic: ST SHIFTER operation ?
Replies: 94
Views: 22758

Re: ST SHIFTER operation ?

Without checking, I'm afraid that the GLUE will only activate /CS for the first 17 of the 32 available addresses. If you try accessing the registers at 0xFF8262-0xFF826E frome code on an STF, do you get a bus error or will the /CS pin on the Shifter be pulled low? If that's the case, a simple way a...
by Smonson
Tue Oct 31, 2017 11:54 pm
Forum: FPGA DEVELOPMENT
Topic: Project: HDMI/DVI out for STFM
Replies: 610
Views: 122024

Project: HDMI/DVI out for STFM

Update: got my boards from the fabricator. 20171101_001158.png.jpeg I still have a bit of fiddling around to get video out of it (I've changed some pins) but it looks like the frame rate instability is still there in 50Hz mode, even though the signals are nice and square. I hypothesise that the reas...
by Smonson
Tue Oct 31, 2017 11:44 pm
Forum: HARDWARE DISCUSSIONS
Topic: ST SHIFTER operation ?
Replies: 94
Views: 22758

Re: ST SHIFTER operation ?

Maybe I should be decoding every individual address from 0-15 and not skipping any address line decoding ?, and the shifter actually then holds another 16 addresses, where the image above is address 16 in the following registers are also internal to the shifter.. Hi Exxos, the shifter gets A1-A5 ra...
by Smonson
Sun Oct 29, 2017 11:52 am
Forum: FPGA DEVELOPMENT
Topic: Project: HDMI/DVI out for STFM
Replies: 610
Views: 122024

Project: HDMI/DVI out for STFM

Here's my current project that's been keeping me up late for several months. Fantastic project! Out of curiosity – would it theoretically possible that this new shifter could handle the higher resolutions of running with 16 MHz, as described in parallel posts, with 1280px hor.? Thanks arf! And the ...

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