Search found 193 matches

by Cyprian
Fri Nov 29, 2019 2:00 pm
Forum: FPGA DEVELOPMENT
Topic: BLITTER RE-CREATION THOUGHTS
Replies: 290
Views: 54830

Re: BLITTER RE-CREATION THOUGHTS

nice news
by Cyprian
Fri Nov 29, 2019 1:58 pm
Forum: SOFTWARE
Topic: Busy Bee in EmuTos
Replies: 12
Views: 2388

Re: Busy Bee in EmuTos

copy files emucurs1.def / emucurs1.rsc to C:\ and rename them to emucurs.def / emucurs.rsc Note that DEF files are useless for EmuTOS itself. They are only used by resource editors to display object names. Just ensure that you have a file C:\EMUCURS.RSC (or A: if you booted from floppy) then everyt...
by Cyprian
Thu Nov 28, 2019 9:46 pm
Forum: SOFTWARE
Topic: Busy Bee in EmuTos
Replies: 12
Views: 2388

Re: Busy Bee in EmuTos

copy files emucurs1.def / emucurs1.rsc to C:\ and rename them to emucurs.def / emucurs.rsc

the same with emuicon0.def / emuicon0.rsc, copy to C:\ and rename them to emuicon.def / emuicon.rsc
by Cyprian
Sat Nov 23, 2019 8:54 pm
Forum: CHAT FORUM
Topic: ACSI
Replies: 5
Views: 811

Re: ACSI

On Jookie's homepage you can find a sources for UltraSatan - ACSI device
http://joo.kie.sk/?page_id=255

what kind of device do you plan?
by Cyprian
Sat Nov 16, 2019 8:04 pm
Forum: CHAT FORUM
Topic: German forums
Replies: 11
Views: 1380

Re: German forums

do you have more info about atari-home.de?

I vote yes.

The more Atari related threads, the better IMO.
by Cyprian
Thu Nov 14, 2019 5:22 pm
Forum: FPGA DEVELOPMENT
Topic: BLITTER RE-CREATION THOUGHTS
Replies: 290
Views: 54830

Re: BLITTER RE-CREATION THOUGHTS

Is there any known difference between the timings of this presumably newer blitter? (functionality wise I assume it's the same). regarding timings, the only known difference is Mega STE, where each blit pass takes one more bus cycle for bus mastering (cache management is suspected of that delay). r...
by Cyprian
Wed Nov 13, 2019 12:32 pm
Forum: FPGA DEVELOPMENT
Topic: BLITTER RE-CREATION THOUGHTS
Replies: 290
Views: 54830

Re: BLITTER RE-CREATION THOUGHTS

What did you try to do and what was the consequence of this? How did this "bug" present itself? I'm interested as I'm messing with the Blitter quiet a lot lately. Thanks, Daniel Below you can find a graphics representation of that behaviour. That screenshot is taken from real hardware. White/grey/r...
by Cyprian
Wed Nov 13, 2019 11:41 am
Forum: FPGA DEVELOPMENT
Topic: BLITTER RE-CREATION THOUGHTS
Replies: 290
Views: 54830

Re: BLITTER RE-CREATION THOUGHTS

On the schematics, it can be seen that the HOG counter counts the XASI signal (incoming AS when the CPU is the bus master, outgoing when the Blitter is), that's how many times the CPU/Blitter accesses the memory. Yeah, it's not implemented this way in Suska. I spent so many hours to find a bug in m...
by Cyprian
Wed Nov 13, 2019 9:40 am
Forum: FPGA DEVELOPMENT
Topic: BLITTER RE-CREATION THOUGHTS
Replies: 290
Views: 54830

Re: BLITTER RE-CREATION THOUGHTS

"Release the bus for 64 CLK cycles." - it uses wrong cycle split scheme I've also changed that back to 64/64. I don't know how the original performs, but my main interest is demo compatibility, which require cycle perfect operation, and it's hard to achieve without having this as a design goal from...
by Cyprian
Tue Nov 12, 2019 8:52 pm
Forum: FPGA DEVELOPMENT
Topic: BLITTER RE-CREATION THOUGHTS
Replies: 290
Views: 54830

Re: BLITTER RE-CREATION THOUGHTS

"Release the bus for 64 CLK cycles." - it uses wrong cycle split scheme

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