Search found 90 matches

by ijor
Sat May 18, 2019 6:11 pm
Forum: ALPHA DEVELOPMENT INFO
Topic: STE DAC FPGA issues
Replies: 16
Views: 4394

Re: STE DAC FPGA issues

You will have to explain what the shifter has to do with the DMA audio... Nothing at all. What I meant is that I'm not sure it is a good idea to implement STE DMA audio in a non STE system. If it is not an STE system, then most software would not detect it as STE and won't use STE sound DMA. It is ...
by ijor
Sat May 18, 2019 5:16 pm
Forum: ALPHA DEVELOPMENT INFO
Topic: STE DAC FPGA issues
Replies: 16
Views: 4394

Re: STE DAC FPGA issues

STE DAC & DMA initially. The suska is essentially a STE. So if I start using the suska cores on the remake project, we are essentially building a STE. The digital side of the DMA is all done in the FPGA core. the DAC side is output by the FPGA via a serial interface to a external DAC chip, which re...
by ijor
Sat May 18, 2019 4:19 am
Forum: ALPHA DEVELOPMENT INFO
Topic: STE DAC FPGA issues
Replies: 16
Views: 4394

Re: STE DAC FPGA issues

IIRC he is doing MMU etc as well, so these could be used on the remake board, but I really do not know how far along he is with all this work ... All the cores are done and complete. Not just MMU and not just the custom chipset, but also MFP, FDC, IKBD, etc. A complete ST system that runs everythin...
by ijor
Sat May 18, 2019 4:15 am
Forum: ALPHA DEVELOPMENT INFO
Topic: STE DAC FPGA issues
Replies: 16
Views: 4394

Re: STE DAC FPGA issues

I am aware of Ijors work on the cores. Ultimately it could used to replace the CPU. I do not know if the FPGA cores can even clock higher than 50MHz. Though for the time being I will just use a real CPU. We can get 50MHz out of it, and I think for a 68000 thats plenty. My 68K core currently has a m...
by ijor
Sat May 18, 2019 4:13 am
Forum: ALPHA DEVELOPMENT INFO
Topic: STE DAC FPGA issues
Replies: 16
Views: 4394

Re: STE DAC FPGA issues

Sorry for the delay. Very busy lately, not much time for Atari, I'm afraid :) ... have been contemplating when the FPGA MMU core etc gets tested with that with it being a STE core, a updated audio DAC circuit will be pretty simple in theory to add to the remake...BUT... When I started looking at the...
by ijor
Mon Feb 11, 2019 7:20 pm
Forum: HARDWARE ISSUES
Topic: STe booster v 1.5 36Mhz
Replies: 88
Views: 14406

Re: STe booster v 1.5 36Mhz

As Ijor pointed out with the slow SND DTACK issues on the STFM, he says this issue was fixed on the STE. I think I should say that I am not 100% sure about that. All I know is I can see the modification and the fix at the STE MCU combo internal schematics (the schematics that Christian recovered). ...
by ijor
Wed Feb 06, 2019 10:52 am
Forum: SEC 64MHZ BOOSTER
Topic: CURRENT PROTOTYPE STATUS (SEC 64MHz 68000)
Replies: 532
Views: 90148

Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

exxos wrote:
Wed Feb 06, 2019 2:33 am
ijor wrote:
Wed Feb 06, 2019 1:36 am
.So are you going to implement shadow ram for copying the rom to ram?
No point is there.
I thought you said flash rom is not fast enough for 50 MHZ without wait states?
by ijor
Wed Feb 06, 2019 1:36 am
Forum: SEC 64MHZ BOOSTER
Topic: CURRENT PROTOTYPE STATUS (SEC 64MHz 68000)
Replies: 532
Views: 90148

Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

45ns SRAM + 10ns PLD delays is about 55ns cycle time. So CPU can run half that (twice as fast) lets just round it to 50ns, so 25ns CPU can run, at 50MHz thats 20ns per cycle (40ns until DTACK) , so basically the SRAM can run at full speed without wait states. I see. I didn't know the PLD was that s...
by ijor
Tue Feb 05, 2019 6:36 pm
Forum: SEC 64MHZ BOOSTER
Topic: CURRENT PROTOTYPE STATUS (SEC 64MHz 68000)
Replies: 532
Views: 90148

Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Even so, even 50MHz is probably way too fast. Look at it that how fast they cycle is now, basically 20ns. Even adding fast ram would mean we would need 10ns RAM which is hard to find and incredibly expensive. I think talked about this previously that I was considering using a small bank of fast ram...
by ijor
Sat Feb 02, 2019 12:11 pm
Forum: SEC 64MHZ BOOSTER
Topic: CURRENT PROTOTYPE STATUS (SEC 64MHz 68000)
Replies: 532
Views: 90148

Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

TOS104 has some "bug" preventing the floppy from being formatted without a initial error. ST TOS uses a software loop to detect timeout on floppy operations. IIRC the loop will timeout in something like a second a half. That is, of course, assuming a stock CPU running at ~8MHz. Formatting a track i...

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