Search found 75 matches

by keli
Tue Feb 20, 2018 12:21 pm
Forum: HARDWARE DISCUSSIONS
Topic: 16BIT ROM CART THOUGHTS
Replies: 139
Views: 18684

Re: 16BIT ROM CART THOUGHTS

So as peter says, we can use LDS OR UDS to switch the ROM's chip enable lines low.. but the question is, does that break anything... My question was that I don't think it would matter, as the CPU will only read high or low byte from the bus anyway, so if we put 16bit data on the bus, it shouldn't m...
by keli
Tue Feb 13, 2018 11:43 pm
Forum: HARDWARE ISSUES
Topic: SCART to HDMI converter
Replies: 7
Views: 2209

Re: SCART to HDMI converter

Some of those cheap HDMI scalers only support composite output. I have one like this: https://www.konigelectronic.com/audio-video/systems-av/hdmi-converter-scart-female-hdmi-output-550581465 These support RGB SCART input and they also have an upscaler. It scales up to full HD. Yes that's the conclu...
by keli
Sat Jan 27, 2018 1:40 am
Forum: ST 16MHz V2.X SERIES BOOSTERS
Topic: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)
Replies: 448
Views: 51276

Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS

Instead of delaying /DTACK by a fixed number of cycles, wouldn't it make more sense to set the delay to be X number of cycles after /AS is asserted? Because the at the original speed the CPU basically ignores the current value of /DTACK until S4 (with /AS asserted in S2).
by keli
Thu Jan 04, 2018 9:04 pm
Forum: ST 16MHz V2.X SERIES BOOSTERS
Topic: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)
Replies: 448
Views: 51276

Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS

How are you handling the two vs three pin bus arbitration protocol translation? Is it handled by the pld or do you simply ignore the /BGACK pin?
by keli
Tue Jan 02, 2018 6:32 am
Forum: EVERYTHING ELSE
Topic: VHDL CACHE ?
Replies: 21
Views: 4739

Re: VHDL CACHE ?

I don't think you'll need a valid bit for every byte of cached memory. You could for instance have larger cache lines. That would impose a bigger delay on initial cache misses but then more would have been fetched on subsequent reads.
by keli
Fri Dec 29, 2017 8:55 am
Forum: EVERYTHING ELSE
Topic: VHDL CACHE ?
Replies: 21
Views: 4739

Re: VHDL CACHE ?

I was reading up on some cache stuff and read similar. Something about instructions been treated as data and it screwing up the self-mod-code. You're describing the situation with internal caches where the instruction and data caches are separate. With an external cache the CPU only sees a faster R...
by keli
Thu Dec 28, 2017 11:20 pm
Forum: EVERYTHING ELSE
Topic: VHDL CACHE ?
Replies: 21
Views: 4739

Re: VHDL CACHE ?

Wouldn't adding cache mean auto modifying code wouldn't work anymore ? probably yes. But every hardware mod done is going to break something, its the price of speed unfortunately. As in this case when the cache is external to the CPU it should be fully transparent and self modifying code should wor...
by keli
Fri Dec 22, 2017 10:51 am
Forum: SOFTWARE PROGRAMMING & DISCUSSION
Topic: HDD drivers. How does it work?
Replies: 14
Views: 2001

Re: HDD drivers. How does it work?

Cache must be not set off in all cases. It is just simple measure to be sure. Problem appears when DMA writes in RAM area what is cached - and cache size is 16 KB on MSTE. Cache is not aware about it, because that write came not from CPU - while cache control is tied only to CPU. So, there will be ...
by keli
Thu Dec 21, 2017 5:00 pm
Forum: HARDWARE DISCUSSIONS
Topic: MNT VA2000 graphics card in a Mega ST
Replies: 11
Views: 3041

Re: MNT VA2000 graphics card in a Mega ST

Hi Kell. Very interesting stuff. As you might know (or not), me and Juliusz have a 68020 board for STE/MSTE with an expansion bus. I was planing on making a video card for it but looking at what you're doing may be we wont and instead support you :) Of course our bus is 32 bits but totally supports...
by keli
Thu Dec 21, 2017 4:01 pm
Forum: HARDWARE DISCUSSIONS
Topic: MNT VA2000 graphics card in a Mega ST
Replies: 11
Views: 3041

Re: MNT VA2000 graphics card in a Mega ST

/DTACK with the clock domain crossing can be more complicated than it seems.. The problem with /DTACK with a lot of the Atari chips is that it can arrive at any time, but, it generally arrives a fraction too early before the data is actually ready to read. Yes all that /DTACK is imo a design flaw w...

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