It might be latching the data too late. According to the 68k manuals, the data may no longer be valid when R/~W is deasserted on a write cycle. Maybe you need to combine your WE with UDS and LDS, which are asserted low while data on the bus is valid?

Yeah I can understand that.. Though high and low byte order, I don't see how it would double the address ? I could ready E00000 and then E00001 on byte access, but I just read E00000 in 16bit and read the lot, so both addresses are accessed at once.. The address number doesn't change.. Edit Even th...

Hmm.. Interesting.. I'm not using LDS,UDS no. Will give it a try when I get home. Yeah your comment on having two roms on the bus gave me the hint. Since you have interleaved bytes from each one, you'll have to double up the addresses. E00000 is byte 0 on the first rom, E00001, byte 0 on the second...

POKEW (&HE05554),&HAAAA POKEW (&HE02AAA),&H5555 POKEW (&HE05554),&H9090 I can't read 5555 because I get address error. So have to use 5554 instead. Wouldn't you have to shift the addresses one bit to the left? I'm assuming you have connected the 68k A1 to the A0 line and are...

I was reminded of the Janus ISA card that contained a 68000, some RAM, and an MFP on a 16 bit ISA card. The card made it possible to run TOS using a 386 PC as a host providing graphics and input. http://www.stcarchiv.de/stc1994/11/janus-atari-emulator From a quick glance at images of the board it lo...

I've been playing around with the Blitter recently and created a PoC implementation of Conway's Game of Life that uses the Blitter for the actual grunt work. I wrote up a blog post about it and posted the source on my website at: https://www.keli.dk/blitter-life/ Why? Because game of life is apparen...

So as peter says, we can use LDS OR UDS to switch the ROM's chip enable lines low.. but the question is, does that break anything... My question was that I don't think it would matter, as the CPU will only read high or low byte from the bus anyway, so if we put 16bit data on the bus, it shouldn't m...

Some of those cheap HDMI scalers only support composite output. I have one like this: https://www.konigelectronic.com/audio-video/systems-av/hdmi-converter-scart-female-hdmi-output-550581465 These support RGB SCART input and they also have an upscaler. It scales up to full HD. Yes that's the conclu...

Instead of delaying /DTACK by a fixed number of cycles, wouldn't it make more sense to set the delay to be X number of cycles after /AS is asserted? Because the at the original speed the CPU basically ignores the current value of /DTACK until S4 (with /AS asserted in S2).

How are you handling the two vs three pin bus arbitration protocol translation? Is it handled by the pld or do you simply ignore the /BGACK pin?