Hi Kell. Very interesting stuff. As you might know (or not), me and Juliusz have a 68020 board for STE/MSTE with an expansion bus. I was planing on making a video card for it but looking at what you're doing may be we wont and instead support you :) Of course our bus is 32 bits but totally supports...

/DTACK with the clock domain crossing can be more complicated than it seems.. The problem with /DTACK with a lot of the Atari chips is that it can arrive at any time, but, it generally arrives a fraction too early before the data is actually ready to read. Yes all that /DTACK is imo a design flaw w...

Update as of 12/21/2017: I started a new HDL project from scratch instead of trying to understand all of the original VA2000 sources, as almost all of the logic was in the top file... most of it in a huge state machine. Instead I've divided everything into small modules talking to each other using t...

A small status update. I managed to solder the sockets on to the adapter board and have done some testing. First the bad news: The bidirectional voltage converters/buffers on the VA2000 all have their /OE pins hardwired to ground. This means that while the FPGA is powering up, its outputs have an un...

I just received the PCB for my adapter. I used ALLPCB and ordered 5 copies for USD 16.00. (Actually received 7) I have all the components, so as soon as I have a few spare clock cycles, I will have to start soldering. pcb 1.jpg I used the footprint for a straight DIN connector for the MegaBus, but a...

AFAIK there is only the palette register, colour changes AFAIK can't reset anything else full screen demos wouldn't work. Possible resolution changes could trigger a internal reset... but again it also would double up that the shifter doesn't output any data for a while and blanking is active for a...

There is also the LGPL licensed TG68 open core. https://opencores.org/project,tg68

Looks interesting! What are the actual specs for the card ? Though assume there will also need to be drivers done for the ST.. It's based on the MiniSpartan6+ and he originally just made an adapter board with just the level converters and sockets for that board. It has later evolved into a board on...

I recently found this open source FPGA graphics card made for the Amiga ZORRO II/III expansion bus . After studying the inner workings of the ZORRO II expansion bus, I noticed it was pretty close to the bare m68000 CPU bus. Feeling brave, I ordered a card from his web shop and now I have a shiny Spa...

Then TOS writes the appropriate video mode value directly into the shifter's video mode register without caching it in a RAM variable The value is in fact cached in RAM at 0x00044C (sshiftmd system variable). Some interrupt handler or handlers reads the shifter's video mode register directly and wr...