I'm assuming LDS UDS might need to be used to ensure there is valid data on the bus. It's not the original data, it's the delay caused by manipulating the data bits when writing the register number to the YM. Originally we know that when BDIR and BC1 are valid, the data bus is already valid (otherw...

With a bit of trying again and again (and making the tri-state gates ideally fast at 0ms) it seems to work sometimes. At least I managed to load into R1 of both YMs 2 different values. i.e. R1 = $19 and R17 = $11 Yes there is probably a timing issue. I think you will have to delay the BC1 and BDIR ...

Here's my latest attempt at doing this correctly. This version should be able to add 3 additional YM chips for a total of 12 audio channels! The first extra chip should replace it's DA4 pin connection with DA4_FLIPPED, the second should connect its DA5 pin to DA5_FLIPPED, and the third one should co...

Yes the YM knows and disables its output, but the buffer used for data reads does not and will drive possibly random data onto the 68000 data bus, as its input will be left floating. That's why I suggested using an analog switch instead for both data reads and writes instead of the tri-state buffers...

Don't you need to memorize which chip got selected (i.e. having that latch somewhere) so when you do register write, the data goes to the correct chip? Or is a bus buffer also memorizing previous state? All 8 address bits are latched inside the YM, so there is no need to store them externally. The ...

Don't you need to memorize which chip got selected (i.e. having that latch somewhere) so when you do register write, the data goes to the correct chip? Or is a bus buffer also memorizing previous state? All 8 address bits are latched inside the YM, so there is no need to store them externally. The ...

Yes definitiely some Windows sytem folders. If I remember correctly, the TOS desktop hides files that have the "system" file attribute set on them, whereas EmuTOS's desk ignores the attribute completely and happily shows them to the unexpecting user.

.... and before I go to bed, here's a solution that uses a 2 to 4 decoder (with inverted outputs) instead of a bunch of nand gates to decode the bus control signals:

Due to the YM going high-impedance when the register address is not correct, the circuit can be much simpler. Leave the original YM (YM0) connected as-is Invert bit 4 on YM1 when BDIR and BC1 are both 1, Connect DA0-3, DA5-7, BDIR, BC1-2, A8, ~A9, etc of YM1 to the same pins as YM0. (the GPIO and an...

Reading the data sheet for the AY-8910 , it seems that General Instrument had a similar scheme in mind: The four low order address bits select one of the 16 registers (R0-R17(base 8)). The six* high order address bits function as "chip selects" to control the tri-state bidirectional buffer...