AS on the CPU will go to Z, but not your ST_AS as it's an output of the CPLD unless you tell it to set it to Z ... by using ST_AS.OE SEC CPU AS -> CPLD -> ST_AS CPU_AS = Z -> CPLD -> ST_AS is either 0 or 1 depending on internal pull-up config and how the CPLD behave when a signal is driven by an inp...

The blitter access the ROM.

That is really weird.
May be I should make a proper one.

On the 68020 card we do have to deal with this and we need to take the BR/BG/BGACK from the ST as well as the ST_AS and CPU_AS to make sure we let the system know when the bus is used by the CPU (68020) and thus assert ST_AS to prevent the glue/GSTMCU from trying to take the bus as there is a bus cy...

If you copied it from another lib in Eagle, make sure you took the TQFP64-10x10 one.

That is really weird. I've used the Eagle TQFP100 and that one was fine. Same with the TQFP44 package. TQFP64 has a pitch of 0.5mm center to center of pins. Pin width should be about 0.20 mm proper dimension can be found in this doc : http://pdf.datasheetcatalog.com/datasheets/134/306806_DS.pdf Make...

It's a DIN 41612 Male type B, 2 rows, 64 position (2x32),2.54mm pitch I think this one is the right one : https://www.mouser.com/ProductDetail/Hirose-Connector/PCN10-64P-254DSA72?qs=sGAEpiMZZMud62t8luTOJovgXPYmPKs4cdlfK7AgVJc%3d Confirmed : https://www.mouser.com/datasheet/2/185/PCN10_catalog-939616...

Yes, I think that the fact it works is mostly because of the GLUE/MMU timing not being changed.

I'm not sure that running the DMA at 16MHz will accelerate any transfer as the GLUE/MMU are the one generating the memory address for the transfer and not the DMA itself (it only has A1 from the address bus). So running it at 16 MHz would only affect the signals generated by the DMA and it might end...