Search found 83 matches

by keli
Wed Sep 06, 2017 12:53 pm
Forum: ALPHA DEVELOPMENT INFO
Topic: CURRENT SCHEMATIC
Replies: 7
Views: 6137

Re: CURRENT SCHEMATIC

How does the RAM circuit select between the upper and lower half of its 32 bit data bus? I looks like you've just connected each pin of the 16 bit bus twice.
by keli
Tue Sep 05, 2017 12:37 pm
Forum: STE V1 SERIES 32MHz BOOSTER
Topic: STE BOOSTER POWERED BY ALTERA TEST
Replies: 7
Views: 8898

Re: STE BOOSTER POWERED BY ALTERA TEST

First of all, excuse me if this has been discussed before, but I have a few questions about speed throttling and the asynchronous nature of the 68000 bus. I notice that all of your boosters (and most other solutions I've seen floating around on the net*) work by lowering the CPU clock frequency when...
by keli
Thu Aug 24, 2017 10:05 am
Forum: FPGA DEVELOPMENT
Topic: BLITTER RE-CREATION THOUGHTS
Replies: 423
Views: 189523

Re: BLITTER RE-CREATION THOUGHTS

I've been scratching my head over these schematics as well. The STE glue/MMC combo schematics contain similar weirdnesses. I think you're right in assuming the multiple inverters were added to fine-tune timing issues and as buffers for fan-out of some signals. (Even though a buffer would have done t...

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