Totally agree. Ranted about it many times myself. People are generally in the "do it for me age". I generally only bother to help people if it looks like they are putting in some effort themselves to start with. My girlfriend is currently correcting about 90+% of mailing addresses, in part...

Here's an updated ramscan which does some extra stuff: Great. Just ran it and it scrolls errors really fast so I cannot really see what address ranges / blocks are bad. There needs to be a "summary page" of some sort. Not sure how 32 bit access works on the thing as the CPU is only physic...

The PSU would not function without R1. It would function without R2. But that is a transient suppressor. If R2 is blown then C6 could also be damaged,

It's R1, sorry for not being more clear about that. Inrush current limiter. Those things are evil and should be banned. They don't age well and do tend to explode like that. I would check the rectifier isn't shorted out to be on the safe side. I'm assuming no other failures in the circuit as well. ...

wub wrote: ↑Sun Nov 13, 2022 11:11 pm Hey Exxos! Yes, there is an official schematic, Mackie are very helpful in providing these on their webpage:

0027370-00-A00-SCH.pdf

Thanks for taking a look, I really appreciate it!

Thanks, which part is it R1, R2 etc ?

But I thought it was organised as 16bit ram, not 32. (In fact its organised as 8bit in terms of addressing but anyway....) The CPU is only has 16bit access to RAM. But the Videl has 32bit access to RAM. Crap isn't it :P I can try that approach next - but it won't be tonight :-p might get some time ...

Is there a schematic ?

I scoped out the RAS/CAS/MADx lines and they all look pretty much perfect overall. IMG_0233.JPG All the spikes are still present on the DATAx signals. I guess the only test I really need to do is work out exactly what address ranges bit11 fails on. Maybe I could impose on dml For a ram test variatio...

I write this down before I forget..This is the way I understand it, which may well be wrong.. MAD8 = 1MB RAM MAD9 = 4MB RAM MAD10 = 16MB RAM. RAS0 = Bits 0-15 RAS1 = Bits 16-31 CAS0L = Bits 0-7 CAS0H = Bits 8-15 CAS1L = Bits 16-23 CAS1H = Bits 24 - 31 So I guess RAS selects a WORD bank and CAS selec...

Confirmed - if I invert bit 11 during the clear/fill operation for ramscan, it shows vertical columns every 16 pixels as you'd expect. So CPU is disagreeing with Videl. somehow. This one has me beat because I don't know how that could happen since the Videl is basically the DRAM controller anyway ....