exxos wrote: ↑Fri Mar 26, 2021 12:58 pm For this particular application, I really would suggest using slower LS types... With them being lower power and slower they are a lot less "noisy".

Alright, I'll take your advice on that too. Thanks again!

exxos wrote: ↑Fri Mar 26, 2021 12:54 pm Yep!

But CE should be OE on the diode signal

Sweet, thanks! Let's just pretend that says OE there. It's just a net name!

I used the GAL to do the address decoding, which controls /OE and the /AS line to run /CE on the ROM. (This matches the timing diagram as /CE should be before /OE.) This meant that the ROM was primed to output whenever an address appeared on the bus. It was then up to the GAL to decode the address ...

exxos wrote: ↑Fri Mar 26, 2021 12:35 pm You can tie CE to GND.. OE is used to enable the ROM.. then put a diode to The same signal with a diode then you can pull DTACK low as well.

Ah, got it. Like this, yeah? (ignoring the signal naming of "CE" which is now misleading)

You don't need to bother with LDS/UDS for ROM. Indeed, UDS and LDS are for writes only. What about /OE though? Just tie it to ground? If you are just using U4 for DTACK.. I really would not bother, just use a diode and tie to ROM_OE... Yes, I believe so. That part is from the schematic provided by ...

Here's my plan for the ROM decoder. These chips are all tiny so it'd all be on top of (or under) the CPU apart from the ROM socket. Is that how other projects have handled LDS/UDS - through an AND gate?

exxos wrote: ↑Mon Mar 15, 2021 10:15 am Yeah that's been a goal mixed in with the 020 CPU.

And make everything 32-bit? Yeah, that would make it simpler, I guess!

Though I hope once we get the cores running on CPU & RAM can run at 32MHz and with our FPGA shifter by @Smonson , we are already ready for higher resolutions and colours. We just need faster RAM, and the suska cores in FPGA opens up this door! A theory - if you're running an FPGA MMU and shifte...

I may need to revisit how they're buffered I guess! Thanks exxos!

Awesome! I wonder why it needed that? The logic signals are buffered so they're supposed to be driven with a decent amount of current. Still, I'm glad you were able to sort it. Looks good now!