you could make the CPU DTACK go back to HI using /ST_AS
CPU_DTACK = DELAYED_DTACK # ST_AS;
ST_AS is your resync CPU_AS to the ST (registered).
DELAYED_DTACK is the DTACK for the CPU after proper delay and force it to go back up when ST_AS get de-asserted (CPU_AS resync'd on 8MHz clock).

Ok, from memory (I don't have time to go dig through the the last 4+ years of email between me and Chris ... over 2100 emails) : GLUE assert DTACK as soon as it decodes a ROM access, expect the CPU to sample it on S4, then de-assert it at the end of S7 as the CPU latch the data on the falling edge o...

While I don't have an answer (yet) I'm too interested in finding a list of filament that match the ST/STE , Mega ST, MegaSTE and TT (which is not grey). I did a quick image search on google for "grey ABS filament" but it's hard to gauge even with a screen that is color calibrated. I looked...

I see, I miss-understood what you were saying (mainly that they were now on layer 1). I they have still been on layer 42 you could have edited the file by hand as it's all XML and the layer values for each element is easy to find. But now that they are on layer 1 it's going to be harder. Can you che...

This means some clearance are not respected. Check your DRC rules, re-run DLC until you either fix the rules or the clearance and they'll go away.

I'll take a PCB, I can assemble it myself

@PaulJ : I stand corrected (I'm always happy to be wrong, it means I'm learning ).

Glad to see other programmer being able to JTAG these devices.

The chipmax2 doesn't .. it does the ATF16/20/22Vxx, ATV750/1500/2500 .. but not the ATF15xx which have their proprietary algo. They require a specific programmer , the ATDH1150USB (which as you can imagine only does these and nothing else). The ATF15xx family : http://ww1.microchip.com/downloads/en/...

Do not mistake register number to data bit on the bus
Register 0 to 7 are 16 bit register, and so are register 8 to 15 and they are accessed as 16 bit registers even if only the lower 8 bit contain actual data for some register.
So CS0 and CS1 select the register bank, not the bus width.