A little bit of context : for my project to replace the ACIAs, I assessed that I needed to use the Enable signal from the 68000 to switch on/off the level translator. And that the switch off should happen between 10ns and 50ns after Enable goes low, according to the MC6850 datasheet.
So I am vaguely remembering that a way to get this delay is to use series of "NOT" gates to accumulate the propagation delays of those gates and obtains the result. I thus plan to use this one (an hex shmitt-triggered inverter) https://www.mouser.fr/ProductDetail/STM ... 2BiQ%3D%3D . I choosed the Schmitt triggered instead of a classic inverter for the histeresys.
and so I have 2 questions :
- Is it the appropriate way to get such delay ?
- The datasheet hints that the propagation delay is dependent to the capacitance of the trace, with 2 datapoints at 15pF (typ. 5.5 ns) and 50pF (typ. 7ns). My traces will be short, especially where I feed one gate output into the input of the next one. Should I plan to add a capacitance (say around 20pF) on each chained output to be sure of the actual delay ?