It is. Among other things it will warn you if some signal on the state machine is not meeting timing. As long as it doesn't, and assuming everything else is correct, it means you are not using too many terms. Of course, you must check the warnings, otherwise you would defeat the whole purpose of this.
Note that this applies only to the internal synchronous logic. This constrain doesn't check the external interface or the asynchronous aspects.
Also it seems the timing analyzer has a bug and can't detect the clock inversion automatically unless you are using a global clock. In this case it doesn't detect the "nexstate" - "state" transfers works on opposite edges.
Even by itself, a simple clock constrain would also help the compiler to optimize the design with a timing-driven compilation. This is much more important on an FPGA design though.