VHDL clocked delay ?

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exxos
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VHDL clocked delay ?

Post by exxos » Thu Feb 20, 2020 4:12 pm

Does anyone have a example on how to delay a signal by a clock ?

Normally I would just Have something like..

FF.CK = CLK_8;
FF.D = input_signal;

So then FF output would be delayed by a CLK_8 (8mhz clock) delay...But how do I program this in VHDL ?


EDIT

Something like this, but I was getting lots of errors :(

Code: Select all

module dff(
    input DE,
    input CLK_8M,
    input RESET_In,
    output DE2
    );
 
always @ (posedge(CLK_8M), posedge(RESET_In))
begin
    if (rst == 1)
        DE2 <= 1'b0;
    else
            DE2 <= DE;
end
 
endmodule
Error (10500): VHDL syntax error at MCU_CONTROL.vhd(157) near text "module"; expecting "begin", or a declaration statement
Error (10500): VHDL syntax error at MCU_CONTROL.vhd(164) near text @
Error (10500): VHDL syntax error at MCU_CONTROL.vhd(166) near text "="; expecting "(", or an identifier, or unary operator
Error (10500): VHDL syntax error at MCU_CONTROL.vhd(167) near text "'"; expecting ";"
Error (10500): VHDL syntax error at MCU_CONTROL.vhd(177) near text "begin"; expecting ";"

EDIT2:

This would make more sense but it does not compile either :roll:

Code: Select all

 signal DE2 	: bit;

begin
if rising_edge(CLK_8M) then
        DE2 <= DE;
end
 
Error (10500): VHDL syntax error at MCU_CONTROL.vhd(160) near text "if"; expecting "end", or "(", or an identifier ("if" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at MCU_CONTROL.vhd(160) near text "then"; expecting "(", or "'", or "."
Error (10500): VHDL syntax error at MCU_CONTROL.vhd(169) near text "begin"; expecting ";", or an identifier ("begin" is a reserved keyword), or "architecture"
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go0se
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Re: VHDL clocked delay ?

Post by go0se » Thu Feb 20, 2020 5:06 pm

Hi Exxos,

I'm no expert but it looks like you're mixing Verilog and VHDL syntax in the above example?

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Re: VHDL clocked delay ?

Post by exxos » Thu Feb 20, 2020 5:11 pm

go0se wrote:
Thu Feb 20, 2020 5:06 pm
I'm no expert but it looks like you're mixing Verilog and VHDL syntax in the above example?
Have no idea, I know zero about this stuff.
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mfro
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Re: VHDL clocked delay ?

Post by mfro » Thu Feb 20, 2020 6:32 pm

exxos wrote:
Thu Feb 20, 2020 4:12 pm
Does anyone have a example on how to delay a signal by a clock ?

Normally I would just Have something like..

FF.CK = CLK_8;
FF.D = input_signal;
the simplest possible way to do that in VHDL would be

Code: Select all

output_signal <= input_signal when rising_edge(clk);
or - more explicit - if you want to do it in a VHDL process:

Code: Select all

process
begin
	wait until rising_edge(clk);
	output_signal <= input_signal;
end process;
And remember: Beethoven wrote his first symphony in C.

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Re: VHDL clocked delay ?

Post by exxos » Thu Feb 20, 2020 8:04 pm

mfro wrote:
Thu Feb 20, 2020 6:32 pm

Code: Select all

output_signal <= input_signal when rising_edge(clk);
With that I get..

Error (10500): VHDL syntax error at MCU_CONTROL.vhd(149) near text "begin"; expecting "entity", or "architecture", or "use", or "library", or "package", or "configuration"
I have of course changed the input,output,clk names to match stuff actually in the code..
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Re: VHDL clocked delay ?

Post by mfro » Thu Feb 20, 2020 8:08 pm

exxos wrote:
Thu Feb 20, 2020 8:04 pm
...
Error (10500): VHDL syntax error at MCU_CONTROL.vhd(149) near text "begin"; expecting "entity", or "architecture", or "use", or "library", or "package", or "configuration"
show the rest of your code. I assume there's something missing or wrong in the entity/architecture framework VHDL requires.

[edit: or did you keep the Verilog code shown above?]
And remember: Beethoven wrote his first symphony in C.

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Re: VHDL clocked delay ?

Post by exxos » Thu Feb 20, 2020 8:09 pm

Code: Select all

use work.MCU_pkg.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity MCU_CONTROL is
	port (  CLK_16M			: in std_logic;
			CLK_8M			: in std_logic;
			RESETn			: in std_logic;

			LDSn, UDSn, RWn	: in bit; -- bus control signals

			M_ADR			: in bit_vector(21 downto 1); -- non multiplexed DRAM adresses
			
			CMPCS_REQ		: in bit; -- request for the shifter data access
			CMPCSn			: out bit; -- control for the shifter data access
			
			RAMn			: in bit; -- RAM access control
			DMAn			: in bit; -- DMA access control

			MEM_CONFIG_CS	: in bit; -- memory config register control
			BANK0_TYPE 		: buffer BANKTYPE; -- memory type indicator
			MCU_PHASE		: out MCU_PHASE_TYPE;
			
			VSYNCn	: in bit; -- vertival sync signal
			DE		: in bit; -- horizontal or vertical sync
			DCYCn	: out bit; -- shifter load signal
					
			RAS0n	: out bit; -- memory bank 1 row adress strobe
			CAS0Hn	: out bit; -- memory bank 1 column adress strobe
			CAS0Ln	: out bit; -- memory bank 1 column adress strobe

			WEn		: out bit; -- memory write control, low active

			RAS1n	: out bit; -- memory bank 2 row adress strobe
			CAS1Hn	: out bit; -- memory bank 2 column adress strobe
			CAS1Ln	: out bit; -- memory bank 2 column adress strobe

			RDATn	: out bit; -- buffer control
			WDATn	: out bit; -- buffer control
			LATCH	: out bit; -- buffer control
			
			REFCNT_EN			: out bit; -- refresh counter enable
			DMA_COUNT_EN		: out bit; -- DMA control
			VIDEO_COUNT_EN		: out bit; -- video control
			VIDEO_COUNT_LOAD	: out bit; -- video control
			
			MADRSEL	: out MADR_TYPE; -- adress multiplexer control

			DTACKn	: out std_logic; -- data acknowledge signal

			DATA	: inout std_logic_vector(7 downto 0)
	);
end MCU_CONTROL;

architecture BEHAVIOR of MCU_CONTROL is
type BANKS is (BANK1, BANK0);
type MATRIX_ELEMENTS is array (1 to 14, 1 to 16) of bit;
constant TIME_MATRIX : MATRIX_ELEMENTS := 
	(('0','0','0','0','0','1','1','0','0','0','0','0','0','1','1','0'),		-- RASn
	 ('1','0','0','0','0','0','0','1','1','0','0','0','0','0','0','1'),		-- CASHn
	 ('1','0','0','0','0','0','0','1','1','0','0','0','0','0','0','1'),		-- CASLn
	 ('0','0','0','0','0','1','1','1','1','1','1','1','1','1','1','0'),		-- WEn
	 ('0','0','0','0','0','0','0','1','1','1','1','1','1','1','1','0'),		-- RDATn
	 ('0','0','0','0','0','1','1','1','1','1','1','1','1','1','1','0'),		-- WDATn
	 ('0','1','1','1','1','0','0','0','0','0','0','0','0','0','0','0'),		-- LATCH
	 ('1','0','0','0','0','1','1','1','1','1','1','1','1','1','1','1'),		-- CMPCSn
	 ('1','1','1','1','1','1','1','1','0','0','0','0','0','0','1','1'),		-- DCYCn
	 ('0','0','0','0','0','1','1','0','0','0','0','0','0','0','0','0'),		-- REFCNT_EN
	 ('0','0','0','0','0','1','1','0','0','0','0','0','0','0','0','0'),		-- DMA_COUNT_EN
	 ('0','0','0','0','0','0','0','0','0','0','0','0','0','1','1','0'),		-- VIDEO_CNT_EN
	 ('0','1','1','1','1','1','1','0','0','1','1','1','1','1','1','0'),		-- MADRSEL
	 ('0','0','0','0','0','0','0','1','1','1','1','1','1','1','1','0'));	-- DTACK_MASKn
signal MCU_PHASE_I			: MCU_PHASE_TYPE;
signal MADRSEL_I			: bit; -- control signal for the high low data multiplexer.
signal MEMCONFIG			: std_logic_vector(7 downto 0);
signal TIME_SLICE_CNT		: std_logic_vector(2 downto 0);
signal SLICE_NUMBER			: integer range 1 to 16;
signal BANK_SWITCH			: BANKS;
signal M_ADR_I 				: bit_vector(23 downto 0);
signal RAS_Pn, RAS_Nn		: bit;
signal CASL_Pn, CASL_Nn		: bit; 
signal CASH_Pn, CASH_Nn		: bit;
signal WE_Pn, WE_Nn			: bit;
signal WDAT_Pn, WDAT_Nn		: bit;
signal DTACK_MASK_In 		: bit;
signal DTACK_MASK_Pn 		: bit;
signal CMPCS_In				: bit;
signal DCYC_Pn, DCYC_Nn		: bit;
signal DCYC_In				: bit;
signal REFCNT_EN_N			: bit;
signal DMA_COUNT_EN_N		: bit;
signal VIDEO_COUNT_EN_N		: bit;
signal DMA_SOUND 			: boolean;

signal DE2	: bit;

--output_signal <= input_signal when rising_edge(clk);

DE2 <= DE when rising_edge(CLK_8M);



begin
DMA_SOUND <= false;
	M_ADR_I <= "00" & M_ADR & '0';
	VIDEO_COUNT_LOAD <= '1' when VSYNCn = '0' else '0';
	MADRSEL <= MEM_LOW_ADR when MADRSEL_I = '0' else MEM_HI_ADR;

	-- bits 3 and 2 of the MEMCONFIG select the bank 0 and the bits
	-- 1 and 0 are for the selection of bank 1.
	BANK0_TYPE <= 	K2048 when MEMCONFIG(3 downto 2) = "10" else
					K512  when MEMCONFIG(3 downto 2) = "01" else
					K128; -- 128K is default

	-- Control signals generated by the two processes SYNC_P and SYNC_N or 
	-- asynchronous. There are four different kinds of generation:
	-- 1. Signals with timings between two different clock edges (e.g. start at
	-- rising edge of CLK_16M and end at falling edge of CLK_16M or vice versa)
	-- are generated by both processes SYNC_P and SYNC_N with logical OR. These
	-- signals are RAS1n, RAS0n, CAS1Hn, CAS1Ln, CAS0Hn, CAS0Ln, WEn, and WDATn. 
	-- 2. Signals embedded between two rising edges of CLK_16M are controlled
	-- by the process SYNC_P. These signals are RDATn, DTACKn and MADR_SEL.
	-- 3. Signals embedded between two falling edges of CLK_16M are controlled
	-- by the process SYNC_N. These signals are LATCH, CMPCSn and the three
	-- counter enables DMA_CNT_EN, REFCNT_EN and VIDEO_CNT_EN.
	-- 4. Signals with a length of only half a period of CLK_16M are controlled 
	-- by both processes and generated by logic AND.
	-- These signals are REFCNT_EN, DMA_COUNT_EN and VIDEO_CNT_EN.
	-- The timing of all these signals is taken from the timing table TIME_MATRIX.
	RAS0n <= 	'0' when (RAS_Pn = '0' and RAS_Nn = '0' and BANK_SWITCH = BANK0) else
				'0' when (MCU_PHASE_I = REFRESH and RAS_Pn = '0' and RAS_Nn = '0') else '1';
	RAS1n <= 	'0' when (RAS_Pn = '0' and RAS_Nn = '0' and BANK_SWITCH = BANK1) else
				'0' when (MCU_PHASE_I = REFRESH and RAS_Pn = '0' and RAS_Nn = '0') else '1';
	CAS0Ln <= 	'0' when CASL_Pn = '0' and CASL_Nn = '0' and BANK_SWITCH = BANK0 else '1';
	CAS1Ln <= 	'0' when CASL_Pn = '0' and CASL_Nn = '0' and BANK_SWITCH = BANK1 else '1';
	CAS0Hn <= 	'0' when CASH_Pn = '0' and CASH_Nn = '0' and BANK_SWITCH = BANK0 else '1';
	CAS1Hn <= 	'0' when CASH_Pn = '0' and CASH_Nn = '0' and BANK_SWITCH = BANK1 else '1';
	WEn <= WE_Pn or WE_Nn;
	WDATn <= WDAT_Pn or WDAT_Nn;
	DCYC_In <= DCYC_Pn or DCYC_Nn;
	-- The following two statements represent the reset functionality of
	-- the original ATARI ST MMU. A better solution is to introduce a global
	-- reset pin in the shifter and also in the MMU when the whole design
	-- GLUE, MMU, BLITTER, SHIFTER and DMA is implemented together in one
	-- COMBO chip.
	DCYCn 	<= '0' when DCYC_In = '0' or RESETn = '0' else '1';
	CMPCSn 	<= '0' when CMPCS_In = '0' or RESETn = '0' else '1';
	DTACK_MASK_In <= DTACK_MASK_Pn;
	REFCNT_EN <= REFCNT_EN_N;
	DMA_COUNT_EN <= DMA_COUNT_EN_N;
	VIDEO_COUNT_EN <= VIDEO_COUNT_EN_N;

	DTACKn <= -- the following conditions are valid for RAM and DMA mode: 
			'0' when MEMCONFIG(3 downto 0) = x"0" and -- 128K in bank 0 and 128K in bank 1 
		 			 M_ADR_I <= x"03FFFE" and M_ADR_I > x"000007" and DTACK_MASK_In = '0'	else
			'0' when MEMCONFIG(3 downto 0) = x"1" and -- 128K in bank 0 and 512K in bank 1
		 			 M_ADR_I <= x"09FFFE" and M_ADR_I > x"000007" and DTACK_MASK_In = '0'	else
			'0' when MEMCONFIG(3 downto 0) = x"2" and -- 128K in bank 0 and 2MB in bank 1
		 			 M_ADR_I <= x"21FFFE" and M_ADR_I > x"000007" and DTACK_MASK_In = '0'	else
			'0' when MEMCONFIG(3 downto 0) = x"4" and -- 512K in bank 0 and 128K in bank 1
		 			 M_ADR_I <= x"09FFFE" and M_ADR_I > x"000007" and DTACK_MASK_In = '0'	else
			'0' when MEMCONFIG(3 downto 0) = x"5" and -- 512K in bank 0 and 512K in bank 1
		 			 M_ADR_I <= x"0FFFFE" and M_ADR_I > x"000007" and DTACK_MASK_In = '0'	else
			'0' when MEMCONFIG(3 downto 0) = x"6" and -- 512K in bank 0 and 2MB in bank 1
		 			 M_ADR_I <= x"27FFFE" and M_ADR_I > x"000007" and DTACK_MASK_In = '0'	else
			'0' when MEMCONFIG(3 downto 0) = x"8" and -- 2MB in bank 0 and 128K in bank 1
		 			 M_ADR_I <= x"21FFFE" and M_ADR_I > x"000007" and DTACK_MASK_In = '0'	else
			'0' when MEMCONFIG(3 downto 0) = x"9" and -- 2MB in bank 0 and 512K in bank 1
		 			 M_ADR_I <= x"27FFFE" and M_ADR_I > x"000007" and DTACK_MASK_In = '0'	else
			'0' when MEMCONFIG(3 downto 0) = x"A" and -- 2MB in bank 0 and 2MB in bank 1
		 			 M_ADR_I <= x"3FFFFE" and M_ADR_I > x"000007" and DTACK_MASK_In = '0'	else
			-- and this one for SHIFTER access mode:
			-- that means HSCROLL register; SHIFTMODE register and PALETTE registers
			'0' when MCU_PHASE_I = SHIFTER and DTACK_MASK_In = '0' else
			'0' when DMAn = '0' and DTACK_MASK_In = '0' else 'Z';

	-- RAM bank select logic. It is dependant on the equiped memory.
	-- The BANK0 is the lower one in the ATARI's adress space.
	BANK_SWITCH <= 
				-- 128Kwords in bank 0:
				BANK0 when BANK0_TYPE = K128  and M_ADR_I <= x"01FFFE" else
				-- 512Kwords in bank 0:
				BANK0 when BANK0_TYPE = K512  and M_ADR_I <= x"07FFFE" else
				-- 2048Kwords in bank 0:
				BANK0 when BANK0_TYPE = K2048 and M_ADR_I <= x"1FFFFE" else
				BANK1;

	MCU_PHASE_CONDITIONING: process(RESETn, CLK_16M)
	-- To adjust the timing of MCU_PHASE with the RAM control signals etc.
	-- it is necessary to delay the MCU_PHASE_I half a period of CLK_16M.
	-- This delay is done in this process.
	begin
		if RESETn = '0' then
			MCU_PHASE <= REFRESH;
		--elsif CLK_16M = '1' and CLK_16M' event then
		elsif rising_edge(CLK_16M) then
			MCU_PHASE <= MCU_PHASE_I;
		end if;
	end process MCU_PHASE_CONDITIONING;

	SYNC_P: process(CLK_16M)
	-- The RASn and CASn multiplexers are implemented in this process as also
	-- the synchronization of the RAM relevant control signals RAS and CAS and WEn.
	-- The BANK_SEL synchronization is not possible due to the fact, that the
	-- BANK_SEL signal appears one CLK cycle too late.
	begin
		--if CLK_16M = '1' and CLK_16M' event then
		if rising_edge(CLK_16M) then
			case MCU_PHASE_I is
				when REFRESH | RAM | VIDEO | SOUND => RAS_Pn <= TIME_MATRIX(1, SLICE_NUMBER);
				when others => RAS_Pn <= '1';
			end case;
			if 	(MCU_PHASE_I = RAM and UDSn = '0') or
				 MCU_PHASE_I = VIDEO or
				 MCU_PHASE_I = SOUND then
					CASH_Pn <= TIME_MATRIX(2, SLICE_NUMBER);		
			else
					CASH_Pn <= '1';
			end if;
			if 	(MCU_PHASE_I = RAM and LDSn = '0') or
				 MCU_PHASE_I = SOUND or
				 MCU_PHASE_I = VIDEO then
					CASL_Pn <= TIME_MATRIX(3, SLICE_NUMBER);		
			else
					CASL_Pn <= '1';
			end if;
			if	MCU_PHASE_I = RAM and RWn = '0' then
					WE_Pn <= TIME_MATRIX(4, SLICE_NUMBER); -- write only in RAM mode.
			else
					WE_Pn <= '1';
			end if;
			if	(MCU_PHASE_I = RAM or MCU_PHASE_I = SHIFTER) and RWn = '1' then
				RDATn <= TIME_MATRIX(5, SLICE_NUMBER); -- read to bus only in RAM mode.
			else
				RDATn <= '1';
			end if;
			if	(MCU_PHASE_I = RAM or MCU_PHASE_I = SHIFTER) and RWn = '0' then
				WDAT_Pn <= TIME_MATRIX(6, SLICE_NUMBER);		
			else
				WDAT_Pn <= '1';
			end if;
			if	MCU_PHASE_I = VIDEO and DE = '1' then
				-- DE is required here due to asynchronous control.
				DCYC_Pn <= TIME_MATRIX(9, SLICE_NUMBER);		
			else
				DCYC_Pn <= '1';
			end if;
			if MCU_PHASE_I = RAM or MCU_PHASE_I = SHIFTER then
				DTACK_MASK_Pn <= TIME_MATRIX(14, SLICE_NUMBER); -- normal RAM access
			else
				DTACK_MASK_Pn <= '1';
			end if;
			MADRSEL_I <= TIME_MATRIX(13, SLICE_NUMBER);
		end if;
	end process SYNC_P;

	SYNC_N: process(CLK_16M)
	begin
		--if CLK_16M = '0' and CLK_16M' event then
		if falling_edge(CLK_16M) then
			case MCU_PHASE_I is
				when REFRESH | RAM | VIDEO | SOUND => RAS_Nn <= TIME_MATRIX(1, SLICE_NUMBER);
				when others => RAS_Nn <= '1';
			end case;
			if 	(MCU_PHASE_I = RAM and UDSn = '0') or
				 MCU_PHASE_I = SOUND or
				 MCU_PHASE_I = VIDEO then
					CASH_Nn <= TIME_MATRIX(2, SLICE_NUMBER);		
			else
					CASH_Nn <= '1';
			end if;
			if 	(MCU_PHASE_I = RAM and LDSn = '0') or
				 MCU_PHASE_I = SOUND or
				 MCU_PHASE_I = VIDEO then
				CASL_Nn <= TIME_MATRIX(3, SLICE_NUMBER);		
			else
				CASL_Nn <= '1';
			end if;
			if	MCU_PHASE_I = RAM and RWn = '0' then
				WE_Nn <= TIME_MATRIX(4, SLICE_NUMBER);		
			else
				WE_Nn <= '1';
			end if;
			if	(MCU_PHASE_I = RAM or MCU_PHASE_I = SHIFTER) and RWn = '0' then
				WDAT_Nn <= TIME_MATRIX(6, SLICE_NUMBER);		
			else
				WDAT_Nn <= '1';
			end if;
			if	MCU_PHASE_I = RAM or MCU_PHASE_I = SHIFTER then
				LATCH <= TIME_MATRIX(7, SLICE_NUMBER);		
			else
				LATCH <= '0';
			end if;
			if	MCU_PHASE_I = SHIFTER then
				CMPCS_In <= TIME_MATRIX(8, SLICE_NUMBER);		
			else
				CMPCS_In <= '1';
			end if;
			if	MCU_PHASE_I = VIDEO and DE = '1' then
				-- DE is required here due to asynchronous control.
				DCYC_Nn <= TIME_MATRIX(9, SLICE_NUMBER);		
			else
				DCYC_Nn <= '1';
			end if;
			if	MCU_PHASE_I = REFRESH then
				REFCNT_EN_N <= TIME_MATRIX(10, SLICE_NUMBER);		
			else
				REFCNT_EN_N <= '0';
			end if;
			if	MCU_PHASE_I = RAM and DMAn = '0' then -- DMA access.
				DMA_COUNT_EN_N <= TIME_MATRIX(11, SLICE_NUMBER);		
			else
				DMA_COUNT_EN_N <= '0';
			end if;
			if	MCU_PHASE_I = VIDEO then
				VIDEO_COUNT_EN_N <= TIME_MATRIX(12, SLICE_NUMBER);		
			else
				VIDEO_COUNT_EN_N <= '0';
			end if;
		end if;
	end process SYNC_N;

	MEMCONFIG_REG: process(RESETn, CLK_8M)
	begin
		if RESETn = '0' then
			-- The MEMCONFIG must start up with x"0A" indicating virtual 4MB RAM.
			-- Otherwise the RAM test routine will hang due to no DTACKn signal.
			-- The value of x"0A" is written immediately after system startup by
			-- the CPU.
			MEMCONFIG <= x"00";
		--elsif CLK_8M = '1' and CLK_8M' event then
		elsif rising_edge(CLK_8M) then
			if MEM_CONFIG_CS = '1' and RWn = '0' then
				MEMCONFIG <= DATA; -- write to register
			end if;
		end if;
	end process MEMCONFIG_REG;
	DATA <= MEMCONFIG when MEM_CONFIG_CS = '1' and RWn = '1' else (others => 'Z'); -- read

	MCU_PHASE_SWITCH: process(RESETn, CLK_16M)
	-- AD MCU_PHASE_TYPES: SHIFTER is foreseen to  access the shifter
	-- registers; VIDEO transfers video data from RAM to shifter; RAM 
	-- is the CPU or DMA to RAM access.
	-- The both REFRESH cycles are to hold the data in the dynamic RAMs.
	-- This process controls the type of data transfer in the second period
	-- of the MCU cycle (250ns ... 500ns). While the first half of the MCU
	-- cycle is reserved for data transfer to the shifter, the second one
	-- shares data transfer between DMA, CPU and RAM and is foreseen for the 
	-- RAM REFRESH process and the data transfer to the shifter registers 
	-- (MCU_PHASE = SHIFTER).
	begin
		if RESETn = '0' then
			MCU_PHASE_I <= REFRESH; -- REFRESH during reset keeps data alive.
		elsif falling_edge(CLK_16M) then
			if SLICE_NUMBER = 7 then
				-- pay attention here! The DMA sound transfer must happen
				-- right after ther falling edge of DE. Otherwise there might
				-- occur synchronisation problems with trash video output.
				-- the DMA sound module must look itself for this correct
				-- timing taking the DE status into account.
				if DE = '0' and DMA_SOUND = true then
					MCU_PHASE_I <= SOUND; -- DMA sound data out.
				else
					MCU_PHASE_I <= VIDEO; -- video data out.					
				end if;
			elsif SLICE_NUMBER = 15 then
				if RAMn = '0' then
					MCU_PHASE_I <= RAM;
				elsif CMPCS_REQ = '1' then
					MCU_PHASE_I <= SHIFTER;
				else -- REFRESH if no data transfer is required.
					MCU_PHASE_I <= REFRESH;
				end if;
			end if;
		end if;
	end process MCU_PHASE_SWITCH;

	TIME_SLICES: process(RESETn, CLK_16M)
	-- the process counts 8 states like the 68000 bus states.
	-- this counter may not have a reset control because it has to
	-- produce refresh timing during reset.
	begin
		-- use the following three lines for simulation or
		-- the fourth one for synthesis -> required for 
		-- refresh signals during system reset.
		--if RESETn = '0' then
		-- TIME_SLICE_CNT <= "000";
		-- elsif CLK_16M = '1' and CLK_16M' event then
		--if CLK_16M = '1' and CLK_16M' event then
		if rising_edge(CLK_16M) then
			TIME_SLICE_CNT <= TIME_SLICE_CNT + '1';
		end if;
	end process TIME_SLICES;

	SLICE_NUMBER <= 1 when TIME_SLICE_CNT = "000" and CLK_16M = '1' else
				    2 when TIME_SLICE_CNT = "000" and CLK_16M = '0' else
				    3 when TIME_SLICE_CNT = "001" and CLK_16M = '1' else
				    4 when TIME_SLICE_CNT = "001" and CLK_16M = '0' else
				    5 when TIME_SLICE_CNT = "010" and CLK_16M = '1' else
				    6 when TIME_SLICE_CNT = "010" and CLK_16M = '0' else
				    7 when TIME_SLICE_CNT = "011" and CLK_16M = '1' else
				    8 when TIME_SLICE_CNT = "011" and CLK_16M = '0' else
				    9 when TIME_SLICE_CNT = "100" and CLK_16M = '1' else
				    10 when TIME_SLICE_CNT = "100" and CLK_16M = '0' else
				    11 when TIME_SLICE_CNT = "101" and CLK_16M = '1' else
				    12 when TIME_SLICE_CNT = "101" and CLK_16M = '0' else
				    13 when TIME_SLICE_CNT = "110" and CLK_16M = '1' else
				    14 when TIME_SLICE_CNT = "110" and CLK_16M = '0' else
				    15 when TIME_SLICE_CNT = "111" and CLK_16M = '1' else
				    16 when TIME_SLICE_CNT = "111" and CLK_16M = '0';
end architecture BEHAVIOR;
EDIT:

It does compile if I move my DE2 line "under" where it says "begin"..
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mfro
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Joined: Thu Dec 13, 2018 7:32 am

Re: VHDL clocked delay ?

Post by mfro » Thu Feb 20, 2020 8:15 pm

got it. The new FF line you added needs to go after the 'begin' statement that follows right below.
And remember: Beethoven wrote his first symphony in C.

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Re: VHDL clocked delay ?

Post by exxos » Thu Feb 20, 2020 8:16 pm

Yep just tried that and compiled :thumbup:
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Re: VHDL clocked delay ?

Post by exxos » Thu Feb 20, 2020 8:26 pm

So how would I do a adjustable delay line ? my effort doesn't compile :(

Code: Select all

begin
signal CLKTMP: std_logic_vector(3 downto 0);

--DE2 <= DE when falling_edge(CLK_8M);

		if rising_edge(CLK_16M) then
				if DE = '0' then	
				CLKTMP <= CLKTMP + '1';
				DE2 <= CLKTMP(2);	
				else DE2 = '1';
			end if 	
		end if;

Or my second failed effort..

Code: Select all

		if rising_edge(CLK_16M) and DE = '0' then
				CLKTMP <= CLKTMP + '1';
				DE2 <= CLKTMP(2);	
				else 
				DE2 = '1';
		end if;



EDIT:

This seems to compile at least now...

Code: Select all

signal DE2	: std_logic;

--output_signal <= input_signal when rising_edge(clk);


signal CLKTMP: std_logic_vector(2 downto 0);

begin


--DE2 <= DE when falling_edge(CLK_8M);

	P1: process (CLK_16M)
    begin


		if rising_edge(CLK_16M) then
		
		if DE = '0' then 	
			CLKTMP <= CLKTMP + '1';
			DE2 <= CLKTMP(2);	
		else 	
			DE2 <= '1';
			--CLKTMP <= '0';
		end if;
		end if;
	end process P1;
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