MEGA ST BLITTER PATCH - Discussion thread

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MEGA ST BLITTER PATCH - Discussion thread

Post by exxos »

blitter_patch.jpg
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MOD.jpg
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If you open a recent Atari ST notice that on 68000 CPU is mounted a small PCB. Here is a modification whose goal is to filter the "Overshoot" of BGACK line.

Blitters Some are so sensitive to "overshoot" they causing "Reset" useless. This phenomenon arises, among others, when the printed SLM804 ~ through ScreenDump devil and programs. The following list blitters that require or not require modification

Code: Select all

Vendor		Date of production	Needed Modification
SGS		before 8823			yes
SGS		after 8822			no
National	before 8908*			yes
National	after 8907			no
GE / RCA	any date			yes
IMP		any date			no

* I had a email from Juliusz saying a 8830 blitter also works ok without the patch. So could be possible Atari made a small mistake on data codes of "problem" blitters.

I'm assuming the 4 number code is YY/WW So 8823 becomes 1988 week 23. Going by a Blitter I have here, it is stamped 9106, so assume 1991 week 6 production and later blitter do not suffer from noise problem. So likely only early MEGA ST's off the production line need the patch.

So again noise on the bus is to blame for chip malfunctions. I guess a alternative method would be to just place some 100R resistors in series with lines which have "overshoot" and that would likely solve the problems without the need to "delay" the signal. It would need testing to prove it.

So do I need this modification? Well likely no, unless you have one of the older ICs which are known to have issues.

It is easy to remove the modification, just simply on solder the board. One thing to bear in mind is there is a track on the bottom of the motherboard PCB which is caught underneath the CPU. If you remove this little board, then you'll need to repair the PCB track.

Source of this research is below.
http://www.exxosforum.co.uk/atari/last/MEGAST/index.htm
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Re: MEGA ST BLITTER PATCH

Post by exxos »

Image below shows the cut trace which gets repaired if you remove the little patch PCB.

IMG_0064.JPG
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With the recovered blitter designs There are two files with two slightly different versions of the blitter. One dated oct 1 1986 and the other dated Mar 18 1988. So basically coincides with the dates in the above post.

Looking at the 2 diagrams. For example.

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and

4021b.JPG
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4051b.JPG
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We can clearly see that inverters have been "hacked in" into the later blitter. But as these problems only seem to be relevant to the MEGA ST which is known to be problematic in various respects. I am making the assumption that the doubling inversions were basically there to filter out noise / spikes which could create false logic levels momentarily. It could equally be possible that the internals of the blitter could have been glitching. As to if these were to add delays or act as noise immunity is difficult to tell without further investigation.

It would be interesting experiment if someone has a older blitter which is proven to cause graphics artefacts as explained on my website. This would of course be without the blitter patch installed. Then change the bus resistors to see if those graphics artefacts disappeared.
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Re: MEGA ST BLITTER PATCH

Post by atari030 »

This might be a dumb question/statement, I assume having the blitter patch fitted to an unaffected blitter will not negatively affect it?

Of all the ST boards I have played with I find the MegaST to be one of the most challenging. They seem to be pretty frail and prone to problems from what I've seen. I was pondering over Steves rebuild and thinking about socketing the CPU in my under repair board and thinking about the patch and they neat way he installed it, a PCB with a SMD IC that sits under the CPU might be a nice idea. Maybe with a TOS decoder and SIMM socket too. :D

I think if there was ever a good candidate for a H5 board, the MegaST is it.
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Re: MEGA ST BLITTER PATCH

Post by ijor »

exxos wrote: Mon Oct 03, 2022 2:18 pm With the recovered blitter designs There are two files with two slightly different versions of the blitter. One dated oct 1 1986 and the other dated Mar 18 1988. So basically coincides with the dates in the above post.

Looking at the 2 diagrams. For example. We can clearly see that inverters have been "hacked in" into the later blitter. But as these problems only seem to be relevant to the MEGA ST which is known to be problematic in various respects. I am making the assumption that the doubling inversions were basically there to filter out noise / spikes which could create false logic levels momentarily.
That is interesting. But both patches are really different things with different purposes, and I'm not sure these modifications have any relation with the Blitter patch, or the Blitter issues on the Mega.

The first patch, the two back to back inverters after the "PB010" NAND seems to be a delay. The second patch, the added inverters that drive the tristate cells (TS5) for the upper nibbles, are buffers, not delays. These inverter buffers are not back to back, they drive separate signals. They were added probably because they determined that the original drivers for these signals (the inverters at the bottom) couldn't properly drive 8 fanouts. This doesn't necessarily means that anything was wrong with the previous version. It could be just a consequence of using a different CMOS process or cells in the new version.

The first patch is really strange. Why they added a delay only for the MSB byte, when the logic is identical for both bytes (MSB and LSB)? Not sure this makes much sense. May be this a buffer that is required for physical, and not logical reasons. Say, the MSB pins and their associated cells might be located further in the die. May be they tried to avoid too much SSN by not switching the output on all data bus pins together. Don't know.
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Re: MEGA ST BLITTER PATCH

Post by alexh »

exxos wrote: Mon Oct 03, 2022 2:18 pm I am making the assumption that the doubling inversions were basically there to filter out noise / spikes which could create false logic levels momentarily. It could equally be possible that the internals of the blitter could have been glitching. As to if these were to add delays or act as noise immunity is difficult to tell without further investigation.
In ASIC design, double inverters are regularly added during layout as delays to fix timing issues.
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Re: MEGA ST BLITTER PATCH

Post by exxos »

ijor wrote: Tue Oct 04, 2022 5:29 am
That is interesting. But both patches are really different things with different purposes, and I'm not sure these modifications have any relation with the Blitter patch, or the Blitter issues on the Mega.
..
The first patch is really strange. Why they added a delay only for the MSB byte, when the logic is identical for both bytes (MSB and LSB)? Not sure this makes much sense. May be this a buffer that is required for physical, and not logical reasons. Say, the MSB pins and their associated cells might be located further in the die. May be they tried to avoid too much SSN by not switching the output on all data bus pins together. Don't know.
There could well be other changes not just those 2. I only quickly looked last night, it was a couple years ago when I first saw the changes. Atari's own documentation stated problems with blitters. So changes done in the blitter *somewhere* indeed fix the issues. As to exactly what they are, what they fix, and why, I cannot really say. Someone would have to do deeper research into it all.
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Re: MEGA ST BLITTER PATCH

Post by exxos »

atari030 wrote: Tue Oct 04, 2022 12:12 am This might be a dumb question/statement, I assume having the blitter patch fitted to an unaffected blitter will not negatively affect it?
It doesn't seem to matter. Atari AFAIK fitted the patch to all MEGA's. I only saw the issues between the "old and new" blitters. The chipset brand used could may well be a issue as to why Atari "blanket fixed" all the machines.
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Re: MEGA ST BLITTER PATCH

Post by ijor »

alexh wrote: Tue Oct 04, 2022 8:37 am In ASIC design, double inverters are regularly added during layout as delays to fix timing issues.
Doesn't seem to be the case here. There are no hold timing issues here that would require to add a delay. This logic is already at the bus interface after the last synchronization. Also I'm not sure these schematics have any layout specific logic. Some of these schematics were even used for Gate Array devices.
exxos wrote: Tue Oct 04, 2022 9:03 am There could well be other changes not just those 2. I only quickly looked last night, it was a couple years ago when I first saw the changes. Atari's own documentation stated problems with blitters. So changes done in the blitter *somewhere* indeed fix the issues. As to exactly what they are, what they fix, and why, I cannot really say. Someone would have to do deeper research into it all.
I was just commenting specifically about those two patches. Yes, there might be other changes, but I checked these schematics some time ago and I don't remember anything relevant. Although to be honest, at that time I looked mostly at the functional behavior.

I do suspect you won't find anything (too) relevant in the schematics. Whatever Atari changed to fix Blitter issues was probably at a different level. They changed manufacturer several times, including probably a different CMOS process. There are also, at least, a couple of versions with different functional behavior that we don't have the schematics. Some time ago I posted a small program to detect a specific variant of Blitter that has a slightly different timing in some cases.
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Re: MEGA ST BLITTER PATCH

Post by exxos »

ijor wrote: Tue Oct 04, 2022 6:05 pm I do suspect you won't find anything (too) relevant in the schematics. Whatever Atari changed to fix Blitter issues was probably at a different level. They changed manufacturer several times, including probably a different CMOS process. There are also, at least, a couple of versions with different functional behavior that we don't have the schematics.
Certainly possible the fab progress or even manufacturer could "fix" the issue. We all know the problems between manufacturers of chips such as IMP etc.

I just found it interesting that there was 2 revisions of the blitter which basically coincided with the dates which Atari had as "good and bad" blitters. As to if those specific logic changes fix the issues or there was other factors involved, I guess we will never know.
ijor wrote: Tue Oct 04, 2022 6:05 pm Some time ago I posted a small program to detect a specific variant of Blitter that has a slightly different timing in some cases.
I don't recall seeing such a program. But was this relating to the manufacture dates of the blitter / brand , or something else ?

I still have the mega motherboard I was doing the testing on but it is in a pitiful state at the moment and I don't know where the original "old" blitter went.
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Re: MEGA ST BLITTER PATCH

Post by ijor »

exxos wrote: Tue Oct 04, 2022 6:27 pm I don't recall seeing such a program. But was this relating to the manufacture dates of the blitter / brand , or something else ?
Yes, the behavior seem to depends on specific Blitter manufacturers. Sorry, I forgot, I posted it in atari-forum:
https://www.atari-forum.com/viewtopic.p ... aff9592bdd

This is a about a (slightly) different functional timing. It shouldn't be directly related to analog issues such as spike, noise, overshoot, etc. But it is perfectly possible that there is some coincidence. None of the schematics reflect this different timing.
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