





I get back "BFBF" as expected now. Its the ID from both flash chips at once on the bus (flash is 8bit wide so 2 chips used to get 16bit)
So it seems...
Data being written to the bus isn't actually valid until UDS/LDS go low

So actually reading the 68K datasheet...

So what I did was to delay the flash for a clock cycle, which basically simulates waiting for LDS,UDS going low.. THEN latch the data on the bus.. What would be happening before would be I would just be latching in 1's all the time as nothing would be driving the bus at that point

Incidentally, I had to use Keli's numbers , so he was right in that I needed to rotate some bits

So we are now talking to the flash


#bobslaw