Looks like I'll be getting a Mega ST4 soon

[exxos]

@exxos I presume this is with the rig in place and no CPU fitted?

So I need to measure the voltage on all the data lines and record the values?

Yes and yes

[rubber_jonnie]

@exxos I presume this is with the rig in place and no CPU fitted?

So I need to measure the voltage on all the data lines and record the values?

Yes and yes

@exxos Cool thanks.

[rubber_jonnie]

@exxos Ok, with no CPU and the pulldown rig in place for the address lines, AS/LDS & UDS, the results are:

D0-D4 = 5.273v
D5-D7 = 5.273v
D8-D12 = 390.6mV
D13-D14 = 5.273V
D15= 390.6mV

I should go see what a working machine is I suppose, but based on what you said earlier:

$60 = %1100000 (high D15-D8)
$2E = %0101110 (low D7 - D0)

Do my results look like the databus is not too pretty? Are you saying D0-D7 should all be low and D8-D15 should all be high? If so, what is responsible for my results? Some logic chip somewhere not doing it's thing?

[exxos]

Do my results look like the databus is not too pretty? Are you saying D0-D7 should all be low and D8-D15 should all be high? If so, what is responsible for my results? Some logic chip somewhere not doing it's thing?

So you have
D15....D8
%01100000

D7....D0
%1111111

That's totally wrong, assuming the ROM's are enabled.. that suggests your ROM's are bad.. But for the lower byte to be all high, could suggest a broken LDS track from CPU to GLUE.

But as also suggested, I would try the same thing on a working machine to verify my pattern is correct first of all..

[rubber_jonnie]

@exxos

I am assuming a 1 = 5.273v and a zero = a reading of 390mV?

If so, then the bad machine looks like this:

D0 D1 D2 D3 D4 D5 D6 D7
1 1 1 1 1 1 1 1

D8 D9 D10 D11 D12 D13 D14 D15
0 0 0 0 0 1 1 0

So what you said:

D15....D8
%01100000

D7....D0
%1111111

I just tested a good machine the same way, results were:

D15....D8
%01100000

D7....D0
%00101110

So it looks like D15-D8 are good, D7-D0 are screwed, hence CPU sitting in a halted state because it isn't getting good code, because it's at the wrong memory location.

Bad Machine
D7....D0
%1111111

Good Machine
D7....D0
%00101110

ROMs were enabled, so CE was low, and I have tested them in another machine, and they are good. If as you say LDS is broken along the way between CPU and GLUE that would make sense given the value for the low bits are wrong.

I'm sure I buzzed that out, but double checking is not a bad idea. I presume a bad connection might also be causing a problem with either resistance or capacitance, even though it could buzz out fine?

[rubber_jonnie]

@exxos I just buzzed out LDS/UDS from GLUE to CPU to MMU and they buzz out fine, so I guess the other question is "What else could set D0-D7 incorrectly?"

In other words,if the connection for UDS/LDS is there, what else could be turning all the data bits to 1 for D0-D7? What else is in the mix?

[exxos]

@rubber_jonnie I assume you have checked CE on both the ROM's ?

EDIT: looks like it be LO-0 ROM.

[Tomswork]

Is there a capacitor shorted some were on the lines

Tom

[PaulJ]

@exxos I just buzzed out LDS/UDS from GLUE to CPU to MMU and they buzz out fine, so I guess the other question is "What else could set D0-D7 incorrectly?"

In other words,if the connection for UDS/LDS is there, what else could be turning all the data bits to 1 for D0-D7? What else is in the mix?

RJ, was this always a 6 rom tos.. did you change it, if so are the w2, w3, w4 set correctly. Do you have the rom in the correct sockets? u3 & u4 pin 20 should show 0 ohms as u6 & u7 pin 20, and u9 and u10.

[stephen_usher]

@exxos I just buzzed out LDS/UDS from GLUE to CPU to MMU and they buzz out fine, so I guess the other question is "What else could set D0-D7 incorrectly?"

In other words,if the connection for UDS/LDS is there, what else could be turning all the data bits to 1 for D0-D7? What else is in the mix?

I take it that you've checked that there are no shorts between the data lines? After this all started when you added the CPU socket.