So, back to this. Yes, the LA shows the 16MHz (first output of the 161) going hi at the same time as MMU 32MHz, however, the second and third outputs of the 161 are not synced to the rising but the falling edge of 16MHz. So, 8MHz never goes hi when 16 does but is always a half 16Mhz cycle behind. The same goes for 4MHz but there I don't think it makes much difference.exxos wrote: ↑Wed Oct 11, 2017 9:14 pmI never checked the sync of the 161, looks to clock on the rising edge and says rising in the pdf after a quick look, your LA seem to clock on the 32mhz HI, so would seem to be all correct I think , glad it proved it could work though! I can add that into the next booster logic now I know it works
I'll think about what signals to study to try to figure out why RAM access is slowed down. If DTACK is done just slightly early then I guess it would cause a halving of throughput.
"A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of CLK."
- SN17F161A: http://www.tij.co.jp/jp/lit/ds/sdfs056b/sdfs056b.pdf
But looking at their state diagram:
... it looks as mine, synced on the falling edge of QA.
FWIW - the way I wired it up is as follows:
- A-D (inputs) to GND
- ENT and ENP to VCC
- CLR and LOAD to VCC