Re: Boosting STFM: 16MHz bus, 64MHz Shifter
Posted: Wed Oct 11, 2017 9:14 pm
Congrats
Not sure why RAM access is 100% ? Possible the overhead from the extra resolution causing it ? I guess only way to find out is to do the DE mod.. Though still would expect RAM to be 200%.. The CPU is running at double speed with the MMU & RAM, so bit odd that.
I never checked the sync of the 161, looks to clock on the rising edge and says rising in the pdf after a quick look, your LA seem to clock on the 32mhz HI, so would seem to be all correct I think , glad it proved it could work though! I can add that into the next booster logic now I know it works
This probably GB3, even so...
.. I don't think its routines would "fake" 200%... GB6 has much better routines, but don't think it would be 100% "out"...
Half asleep here, but my first thought is the MMU would trigger DTACK double speed, CPU would read at double speed.. nothing to generate waitstates unless the CPU totally missed DTACK for ages. Even if it missed by half a clock cycle, would still expect 150% or more.
So my initial thought is the extra resolution must be hogging MMU time with display updates, and lowering the RAM speed test back to 100%..
Wonder if you could simply load GB6, and disconnect the DE signal, screen will not update of course, but if you leave the signal disconnected (tie to 0v) just for testing, press "A" to run all tests, then wait a couple of moments, and reconnect DE , then you can see the results.. might even get 400% then Idea being just to "turn off" the shifter requesting MMU time..
Not sure why RAM access is 100% ? Possible the overhead from the extra resolution causing it ? I guess only way to find out is to do the DE mod.. Though still would expect RAM to be 200%.. The CPU is running at double speed with the MMU & RAM, so bit odd that.
I never checked the sync of the 161, looks to clock on the rising edge and says rising in the pdf after a quick look, your LA seem to clock on the 32mhz HI, so would seem to be all correct I think , glad it proved it could work though! I can add that into the next booster logic now I know it works
This probably GB3, even so...
.. I don't think its routines would "fake" 200%... GB6 has much better routines, but don't think it would be 100% "out"...
Half asleep here, but my first thought is the MMU would trigger DTACK double speed, CPU would read at double speed.. nothing to generate waitstates unless the CPU totally missed DTACK for ages. Even if it missed by half a clock cycle, would still expect 150% or more.
So my initial thought is the extra resolution must be hogging MMU time with display updates, and lowering the RAM speed test back to 100%..
Wonder if you could simply load GB6, and disconnect the DE signal, screen will not update of course, but if you leave the signal disconnected (tie to 0v) just for testing, press "A" to run all tests, then wait a couple of moments, and reconnect DE , then you can see the results.. might even get 400% then Idea being just to "turn off" the shifter requesting MMU time..