Possibly:
- ROM A0
- ROM A1
- ROM A2
- ROM A3
- ROM /CE
- ROM /OE
- CPU /HALT
- CPU /BERR
- CPU /AS
- CPU /DTACK
- CPU /UDS
- CPU /LDS
- CPU R/W
- CPU A1
- CPU A2
- CPU A3
CH12 is A12.
I have 16 channels so this is possible. There is no A0 at the ROM, just A1 to A15, however since ROM /CE is no longer getting a signal at all from the GLUE/MMU combo, that is a worry, since there is no signal at the pin of the IC.stephen_usher wrote: ↑Tue Jan 25, 2022 2:09 pm Depending upon how many channels your LA has, I'd suggest only monitoring the bottom few address lines on the address bus as they'll be the most active. You can then use the other lines for the control lines, which are just as important, maybe more so.
Possibly:This should show both ends of the bus and whether the MMU is selecting the ROM correctly and if you have real connectivity on the lowest address lines.
- ROM A0
- ROM A1
- ROM A2
- ROM A3
- ROM /CE
- ROM /OE
- CPU /HALT
- CPU /BERR
- CPU /AS
- CPU /DTACK
- CPU /UDS
- CPU /LDS
- CPU R/W
- CPU A1
- CPU A2
- CPU A3
Does HALT stay high without the CPU fitted ?rubber_jonnie wrote: ↑Tue Jan 25, 2022 2:33 pm /RESET - goes high at power on, and low then high when reset is pressed. Seems normal.
/BERR - goes high at power on, with a quick dip low, then back to high. Dips low and goes back high on reset.
/HALT - Goes high at power on then low - CPU is halted in that case. Reset is the same.
AS - Goes high on power up, low on reset.
/DTACK - Goes high on power up, then briefly low and back to high. The same on reset.
Nope, it goes high briefly then drops low again, which is effectively showing the CPU as stopped.
Sorry, I misread your post.exxos wrote: ↑Tue Jan 25, 2022 3:57 pmDoes HALT stay high without the CPU fitted ?rubber_jonnie wrote: ↑Tue Jan 25, 2022 2:33 pm /RESET - goes high at power on, and low then high when reset is pressed. Seems normal.
/BERR - goes high at power on, with a quick dip low, then back to high. Dips low and goes back high on reset.
/HALT - Goes high at power on then low - CPU is halted in that case. Reset is the same.
AS - Goes high on power up, low on reset.
/DTACK - Goes high on power up, then briefly low and back to high. The same on reset.
The UM saysrubber_jonnie wrote: ↑Tue Jan 25, 2022 5:01 pm With the CPU fitted, /HALT goes high on power up or reset, then drops low, so the /HALT seems to be coming from the CPU, which would be the case if it couldn't boot.
With the CPU removed, /HALT goes high on power up and stays there until reset is pressed, then it drops low and back up to high.
So the CPU is trying to access an address which isn't responding. IE ROM. But this means the combel isn't decoding address zero. That is the very first CPU function, where the address bus should all be low like in your working setup. Though IIRC the CPU puts the first address on the bus. But it's like the CPU isn't running, like a missing clock to it.Double Bus Fault
When a bus error exception occurs, the processor begins exception processing by
stacking information on the supervisor stack. If another bus error occurs during exception
processing (i.e., before execution of another instruction begins) the processor halts and
asserts HALT. This is called a double bus fault. Only an external reset operation can
restart a processor halted due to a double bus fault.
exxos wrote: ↑Tue Jan 25, 2022 6:09 pmThe UM saysrubber_jonnie wrote: ↑Tue Jan 25, 2022 5:01 pm With the CPU fitted, /HALT goes high on power up or reset, then drops low, so the /HALT seems to be coming from the CPU, which would be the case if it couldn't boot.
With the CPU removed, /HALT goes high on power up and stays there until reset is pressed, then it drops low and back up to high.
So the CPU is trying to access an address which isn't responding. IE ROM. But this means the combel isn't decoding address zero. That is the very first CPU function, where the address bus should all be low like in your working setup. Though IIRC the CPU puts the first address on the bus. But it's like the CPU isn't running, like a missing clock to it.Double Bus Fault
When a bus error exception occurs, the processor begins exception processing by
stacking information on the supervisor stack. If another bus error occurs during exception
processing (i.e., before execution of another instruction begins) the processor halts and
asserts HALT. This is called a double bus fault. Only an external reset operation can
restart a processor halted due to a double bus fault.
Again, It may just be easier to hardwire the lines as I mentioned previously to 0v and just remove the CPU. You could probably just hardwire some bodge wires on top of the ROM chip to wire most of the address bus low. Finish off with the upper address bus and AS,UDS,LDS hardwired on the bottom of the CPU socket.
This way, when you power up, the entire bus is pulled low, the combel will decode that address and issue CE on the ROM. If it's not doing that, then either a address is missing on the combel, or possibly the combel is faulty. In which case, it's pretty much game over at that point anyway.
I think you possibly have multiple issues going on. Because at this point it is like the CPU is not running, and you don't even know if it is even trying to decode the ROM start address. You need to rule something out.. IMO Trying to diagnose if the combel is even functioning at all is probably the best bet. Because if you cannot get that working, then there's no point trying to diagnose anything else anyway.