Brett's STE - Repair thread

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stephen_usher
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Re: Brett's STE - Repair thread

Post by stephen_usher »

Depending upon how many channels your LA has, I'd suggest only monitoring the bottom few address lines on the address bus as they'll be the most active. You can then use the other lines for the control lines, which are just as important, maybe more so.

Possibly:
  • ROM A0
  • ROM A1
  • ROM A2
  • ROM A3
  • ROM /CE
  • ROM /OE
  • CPU /HALT
  • CPU /BERR
  • CPU /AS
  • CPU /DTACK
  • CPU /UDS
  • CPU /LDS
  • CPU R/W
  • CPU A1
  • CPU A2
  • CPU A3
This should show both ends of the bus and whether the MMU is selecting the ROM correctly and if you have real connectivity on the lowest address lines.
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Re: Brett's STE - Repair thread

Post by rubber_jonnie »

exxos wrote: Tue Jan 25, 2022 11:49 am Whats on chan 12 ?

Can you post, RESET, BERR,HALT, AS, DTACK,

It looks like the CPU is not running.
CH12 is A12.

/RESET - goes high at power on, and low then high when reset is pressed. Seems normal.
/BERR - goes high at power on, with a quick dip low, then back to high. Dips low and goes back high on reset.
/HALT - Goes high at power on then low - CPU is halted in that case. Reset is the same.
AS - Goes high on power up, low on reset.
/DTACK - Goes high on power up, then briefly low and back to high. The same on reset.

Interesting you say the CPU is not running, because I get the same error screen (Thin black line at the top and the rest white) when I run my own STE with no CPU. Or no ROM for that matter.

CPU clock is good at 8Mhz. CPU works in my STE too. I think it is running, just /HALTed.

For some reason, it's now stopped giving /CE pulses at all now. I traced it back across to pin 9 of the GST MMU/GLUE, and there's no /CS at there.

That is not a good sign, as it was working until yesterday....
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Re: Brett's STE - Repair thread

Post by rubber_jonnie »

stephen_usher wrote: Tue Jan 25, 2022 2:09 pm Depending upon how many channels your LA has, I'd suggest only monitoring the bottom few address lines on the address bus as they'll be the most active. You can then use the other lines for the control lines, which are just as important, maybe more so.

Possibly:
  • ROM A0
  • ROM A1
  • ROM A2
  • ROM A3
  • ROM /CE
  • ROM /OE
  • CPU /HALT
  • CPU /BERR
  • CPU /AS
  • CPU /DTACK
  • CPU /UDS
  • CPU /LDS
  • CPU R/W
  • CPU A1
  • CPU A2
  • CPU A3
This should show both ends of the bus and whether the MMU is selecting the ROM correctly and if you have real connectivity on the lowest address lines.
I have 16 channels so this is possible. There is no A0 at the ROM, just A1 to A15, however since ROM /CE is no longer getting a signal at all from the GLUE/MMU combo, that is a worry, since there is no signal at the pin of the IC.

I'll hook it all up as you suggest, probably tomorrow as out tonight. The trace from the GST IC (Pin 9) does go all the way back to the ROM sockets OK BTW and was fine just yesterday.
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Re: Brett's STE - Repair thread

Post by rubber_jonnie »

Ok, so the /CE no longer working problem is resolved. Phew.

I reseated all the socketed chips, and nothing changed until I reseated the Blitter. Once that was done, I started getting /CE back again. I can only assume it had moved on account of me handling the board.

Still doesn't boot, but since I need to test the Blitter anyway, I may as well just get on and do so since it's brought attention to itself.
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Re: Brett's STE - Repair thread

Post by exxos »

rubber_jonnie wrote: Tue Jan 25, 2022 2:33 pm /RESET - goes high at power on, and low then high when reset is pressed. Seems normal.
/BERR - goes high at power on, with a quick dip low, then back to high. Dips low and goes back high on reset.
/HALT - Goes high at power on then low - CPU is halted in that case. Reset is the same.
AS - Goes high on power up, low on reset.
/DTACK - Goes high on power up, then briefly low and back to high. The same on reset.
Does HALT stay high without the CPU fitted ?
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Re: Brett's STE - Repair thread

Post by rubber_jonnie »

exxos wrote: Tue Jan 25, 2022 3:57 pm
Does HALT stay high without the CPU fitted ?
Nope, it goes high briefly then drops low again, which is effectively showing the CPU as stopped.
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Re: Brett's STE - Repair thread

Post by rubber_jonnie »

exxos wrote: Tue Jan 25, 2022 3:57 pm
rubber_jonnie wrote: Tue Jan 25, 2022 2:33 pm /RESET - goes high at power on, and low then high when reset is pressed. Seems normal.
/BERR - goes high at power on, with a quick dip low, then back to high. Dips low and goes back high on reset.
/HALT - Goes high at power on then low - CPU is halted in that case. Reset is the same.
AS - Goes high on power up, low on reset.
/DTACK - Goes high on power up, then briefly low and back to high. The same on reset.
Does HALT stay high without the CPU fitted ?
Sorry, I misread your post.

With the CPU fitted, /HALT goes high on power up or reset, then drops low, so the /HALT seems to be coming from the CPU, which would be the case if it couldn't boot.

With the CPU removed, /HALT goes high on power up and stays there until reset is pressed, then it drops low and back up to high.
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800XL and 65XE both with Ultimate1MB,VBXL/XE & PokeyMax, SIDE3, SDrive Max, 2x 1010 cassette, 2x 1050 one with Happy mod, 3x 2600 Jr, 7800 and Lynx II
Approx 20 STs, including a 520 STM, 520 STFMs, 3x Mega ST, MSTE & 2x 32 Mhz boosted STEs
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Re: Brett's STE - Repair thread

Post by exxos »

rubber_jonnie wrote: Tue Jan 25, 2022 5:01 pm With the CPU fitted, /HALT goes high on power up or reset, then drops low, so the /HALT seems to be coming from the CPU, which would be the case if it couldn't boot.

With the CPU removed, /HALT goes high on power up and stays there until reset is pressed, then it drops low and back up to high.
The UM says
Double Bus Fault
When a bus error exception occurs, the processor begins exception processing by
stacking information on the supervisor stack. If another bus error occurs during exception
processing (i.e., before execution of another instruction begins) the processor halts and
asserts HALT. This is called a double bus fault. Only an external reset operation can
restart a processor halted due to a double bus fault.
So the CPU is trying to access an address which isn't responding. IE ROM. But this means the combel isn't decoding address zero. That is the very first CPU function, where the address bus should all be low like in your working setup. Though IIRC the CPU puts the first address on the bus. But it's like the CPU isn't running, like a missing clock to it.

Again, It may just be easier to hardwire the lines as I mentioned previously to 0v and just remove the CPU. You could probably just hardwire some bodge wires on top of the ROM chip to wire most of the address bus low. Finish off with the upper address bus and AS,UDS,LDS hardwired on the bottom of the CPU socket.

This way, when you power up, the entire bus is pulled low, the combel will decode that address and issue CE on the ROM. If it's not doing that, then either a address is missing on the combel, or possibly the combel is faulty. In which case, it's pretty much game over at that point anyway.

I think you possibly have multiple issues going on. Because at this point it is like the CPU is not running, and you don't even know if it is even trying to decode the ROM start address. You need to rule something out.. IMO Trying to diagnose if the combel is even functioning at all is probably the best bet. Because if you cannot get that working, then there's no point trying to diagnose anything else anyway.
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Re: Brett's STE - Repair thread

Post by rubber_jonnie »

exxos wrote: Tue Jan 25, 2022 6:09 pm
rubber_jonnie wrote: Tue Jan 25, 2022 5:01 pm With the CPU fitted, /HALT goes high on power up or reset, then drops low, so the /HALT seems to be coming from the CPU, which would be the case if it couldn't boot.

With the CPU removed, /HALT goes high on power up and stays there until reset is pressed, then it drops low and back up to high.
The UM says
Double Bus Fault
When a bus error exception occurs, the processor begins exception processing by
stacking information on the supervisor stack. If another bus error occurs during exception
processing (i.e., before execution of another instruction begins) the processor halts and
asserts HALT. This is called a double bus fault. Only an external reset operation can
restart a processor halted due to a double bus fault.
So the CPU is trying to access an address which isn't responding. IE ROM. But this means the combel isn't decoding address zero. That is the very first CPU function, where the address bus should all be low like in your working setup. Though IIRC the CPU puts the first address on the bus. But it's like the CPU isn't running, like a missing clock to it.

Again, It may just be easier to hardwire the lines as I mentioned previously to 0v and just remove the CPU. You could probably just hardwire some bodge wires on top of the ROM chip to wire most of the address bus low. Finish off with the upper address bus and AS,UDS,LDS hardwired on the bottom of the CPU socket.

This way, when you power up, the entire bus is pulled low, the combel will decode that address and issue CE on the ROM. If it's not doing that, then either a address is missing on the combel, or possibly the combel is faulty. In which case, it's pretty much game over at that point anyway.

I think you possibly have multiple issues going on. Because at this point it is like the CPU is not running, and you don't even know if it is even trying to decode the ROM start address. You need to rule something out.. IMO Trying to diagnose if the combel is even functioning at all is probably the best bet. Because if you cannot get that working, then there's no point trying to diagnose anything else anyway.

Ok, so my brain is a bit fried due to training, it being gone midnight and some crappy stuff going on with my parents!!!

I strongly suspect that the weird stuff with the Blitter (Now tested as good), like the total failure of the combel to issue a /CE at all, may have been causing the LA recording to be off, so I need to check that again and compare to the working machine, plus trying what both you and Stephen have suggested.

I agree that if the combel is dead, then it is game over, but now I've reseated the Blitter and it is now giving a /CE pulse on startup and reset, then I need to see what the address bus is doing. If I can do that with the LA fine, if not then I will look at hardwiring as you've suggested.

My current theory is that it's still the ROM connections, so either the address bus has the right signals, but the data bus is garbled and the CPU is going into a /HALTed state, or the address on the bus is incorrect, and the data coming out is incorrect and the CPU is going into a /HALTed state, or a combination of both.

I will have a look tomorrow evening.
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800XL and 65XE both with Ultimate1MB,VBXL/XE & PokeyMax, SIDE3, SDrive Max, 2x 1010 cassette, 2x 1050 one with Happy mod, 3x 2600 Jr, 7800 and Lynx II
Approx 20 STs, including a 520 STM, 520 STFMs, 3x Mega ST, MSTE & 2x 32 Mhz boosted STEs
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Re: Brett's STE - Repair thread

Post by olivier.jan »

Sorry if this sounds stupid, but did you check the motherboard jumpers are set correctly for the type of ROM you’re using ?
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