STE V1.5 32MHz BOOSTER - STATUS

Help & information about the STE V1 series boosters.
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Re: STE V1.5 32MHz BOOSTER - STATUS

Post by exxos »

Forgottenmyname wrote: Wed Apr 11, 2018 10:02 pm I understand most of it. In reality I've been re-learning electronics by fixing computers.
Even found myself reading a Dram data sheet the other day to verify the waveform i was seeing... how sad is that :lol:
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Re: STE V1.5 32MHz BOOSTER - STATUS

Post by exxos »

Doing some more 40MHz tests.. Still getting to stability issues.. Seems it mostly locks up on ROM test, but even bypassing "fast rom" (8mhz used) it still fails.

So I thought I would try the YAART cartridge to see if the CPU can loop though RAM without crashing (trying to work out if the CPU is maxing out or not). Interesting thing is, on power up, I got "WARNING BAD ROM CHIP" error... So I think the extra load on the bus is pushing it over the edge..

So tomorrow I might add some less resistance to the address & databus.. see if that prevents the error.. it could be pull up issues as to why 40MHz is unstable ( I have 2.2K plus original 10K at the moment so ~1.8K). Another 10K would be about 1.5K total..

It's probably the address bus at fault.. as while reading ROM (speed test) data is relevant.. it just reads the same address over and over.. but if the address is "wrong" it could cause a bus error and crash..
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Re: STE V1.5 32MHz BOOSTER - STATUS

Post by exxos »

I had it looping on memory test for about an hour last night and it ran fine at 40 MHz. So I think the CPU can actually run at this speed without issues. However I was still getting intermittent crashes during ROM access.

So today I added in a extra 10k resistor pack onto the address bus. When the diagnostic cartridge is in place it no longer triggers the ROM error. However, it was still crashing on ROM test pretty much all the time, and intermittently during mostly VDI text tests.

So next I added in a extra 10k onto the databus, and currently (now I am just going to jinx this :lol: ) 5 full test loops on GB6. Before it would only do one or two without crashing.

So currently the address bus has 4.7K (stock) + 2.2K + 10K = 1.3K.
The databus has 10K (stock) + 2.2K + 10K = 3.3K.

IMG_2419.JPG
IMG_2419.JPG (60.18 KiB) Viewed 4802 times

EDIT:
OK it crashed on loop 6 :roll:

So I will remove the 10k the databus and use a 4.7K this time.
10K (stock) +2.2K +4.7K = 1.3K


EDIT2:
I still have some stability issues seems :roll: so I have gone back to the start and removed the ROM chip select line ,so the ROM runs at 8 MHz. This ran for about half an hour so I seen this is now stable, which it wasn't before. So obviously changing the resistor packs as improved things a little bit least.

So I have gone back to adding in some DTACK delays onto the ROM access... And now it seems looking a very slow loop of drawing and clearing these pixel line is one of the tests... :shrug:

c1.jpg
c1.jpg (59.02 KiB) Viewed 4791 times


Overall the benchmark figures are slower than the 35 MHz tests which is actually stable.. So I'm not sure what I am missing with all this :shrug:

I'm starting to wonder if the ROM chip select signal is falsely going low due to some noise on the bus, or simply a glitch in the GLUE logic. It would only have to go low for a few ns to switch the booster into high-speed which could be causing the random lock-ups. So likely later I will try running the ROM chip select line through a couple of delays so that any glitches should be ignored..

Currently I have disabled the reset code in the GAL. Normally when you press reset button it forces the GAL to 8 MHz mode. With this removed, I had trouble getting the machine to boot up, but now it is looping through all the tests again and we shall see what happens this time.. I'm thinking possibly even the reset line would glitch just enough to throw the booster into switching speeds when it's not supposed to be. Of course this should not actually matter as the switching should go to 8 MHz anyway.. But as this is a reset for a FF , then it could be possible it could glitch the CPU clock... But leave no stone unturned as they say...

EDIT3:

So reset is not a issue..
I also currently have about 50ns delay on DTACK and ROM_CS.. Still it is not stable.. :shrug:

I would basically think that the ROM chip itself not fast enough.. I know the timings were very tight when I was doing 32 MHz. So maxing out at 35 MHz makes sense.. 40 MHz simply pushes it over the edge... But this should be counteracted by slowing down DTACK giving the ROM more time to settle before CPU reads the bus ... But this does not seem to be working, and I have checked that the delays are there.. I think if anything is now working worse now ROM_CS is delayed..

So I will one do the changes and go back to the best working code.. But how it looks, I do not think 40 MHz is simply going to work for some reason :(

Anything could possibly be is that the CPU can run for short bursts at 40 MHz, but with the ROM in the mix as well, the CPU runs at 40 MHz more times, so maybe this simply pushes the CPU over the edge.. I guess I could take out /AS from the equations and only run the CPU faster when accessing ROM to prove this or not...

EDIT4:
So only running the ROM at 40 MHz also fails :shrug:

It could be similar noise problems as I found with the DMA circuit. Whereas accessing the DMA directly causes no issue, but when mixing in ROM access, it creates noise and ground bounces all over the place and then causes a issue. Also testing the ROM on its own will also test perfectly well.

So I suspect this problem I now have could likely be similar issue. Of course investigating this would take a phenomenal amount of time where I don't think it is worth investigating. I will do some more tests tomorrow but then I think I will call it a day and trying to get the CPU to run at 40 MHz. I will likely just backtrack to 35MHz or 38MHz on the final design to play it safe.
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Re: STE V1.5 32MHz BOOSTER - STATUS

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So further to all the chaos above today.. Decided as slowing things down seem to progressively make things worse, I decided to speed things up instead.. Of course running something faster when it is unstable should logically make it more unstable shouldn't it ?!

While I was at it I added in "predictive ROM read technology" , and makes something I did which was incredibly simple sound totally awesome :lol:

So far the results seem to have jumped up a bit...

40mhz_new.jpg
40mhz_new.jpg (104.85 KiB) Viewed 4772 times

And the original below..

40WSv2.jpg
40WSv2.jpg (106.41 KiB) Viewed 4772 times

.. Now to see how long it takes before it crashes again :lol: ironically it seems more stable than it was earlier :shrug:
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Re: STE V1.5 32MHz BOOSTER - STATUS

Post by rpineau »

"predictive ROM read technology" .. LOL ... /CS to ground and only use /OE for selection ? :D

In any case ... looks fast !
RoRo
Working ones : MegaSTE (68020) / TT030 / Falcon with AB040 & Eclipse / 1040STF
Need testing : Falcon with CT2
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Re: STE V1.5 32MHz BOOSTER - STATUS

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rpineau wrote: Thu Apr 12, 2018 10:10 pm /CS to ground and only use /OE for selection ? :D
That was already done in V1 ;) But a good guess :)
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Re: STE V1.5 32MHz BOOSTER - STATUS

Post by rpineau »

Ok, then next thing that comes to mind is to not use /AS to validate so that you can assert /OE as soon as the address match the TOS :)
Working ones : MegaSTE (68020) / TT030 / Falcon with AB040 & Eclipse / 1040STF
Need testing : Falcon with CT2
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Re: STE V1.5 32MHz BOOSTER - STATUS

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rpineau wrote: Fri Apr 13, 2018 2:31 am Ok, then next thing that comes to mind is to not use /AS to validate so that you can assert /OE as soon as the address match the TOS :)
Nope :)

This is original ROM access...
r2.png
r2.png (4.74 KiB) Viewed 5063 times

And with the predictive ROM read technology..
r1.png
r1.png (4.6 KiB) Viewed 5063 times

This actually gives me a idea.. That possibly I could just run the CPU at 40 MHz all the time, and only switch down to 8Mhz when doing 6800 cycles..
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Re: STE V1.5 32MHz BOOSTER - STATUS

Post by exxos »

It seems fate is telling me it is time to do a new PCB.. :roll:

Snapping the DTACK pin of the CPU probably did not help much :lol: even after trying to tack it back on I just keep getting bombs. When it did work, machine ran 50% slower :roll:

cs.jpg
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Re: STE V1.5 32MHz BOOSTER - STATUS

Post by exxos »

New PCB layout :)

A few mods and tweaks here and there. Added in a 3.3V regulator and oscillator. Done the DTACK routing via the GAL. Also rooted VMA, VPA just in case I want to experiment later.

I use a small schmitt buffer to clean up the GAL output to the CPU clock. One thing I have not been able to figure out is that it only works with a 220R resistor from the GAL output to the buffer input. The output of the buffer exactly the same regardless of resistor use. But any other value and machine refuses to boot. The only difference is that the resistor lessens the voltage to the input of the buffer.. So no idea what is going on there.

I found a different buffer it is not a schmitt one, I do not think this is really needed anyway, but the new buffer does not register a logic one until about 3.8V. The GAL output does have a small glitch, so this gives a huge hysteresis voltage which should act better than a schmitt buffer in this case.

Also done some minor PCB rerouting in a few places. So now this board is ready to order I think, so I will likely order it next week. Then it's back to waiting for PCBs to arrive again :roll:

REVD.jpg
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