I have had a motherboard in for some time trying to figure out why boosters are unstable on it.. It is one of the more later boards with integrated blitter. I did ask around before and no one else had any problems with the boosters with this particular style of motherboard. Though this one has been a royal PITA.
I first thought there was some issue with the blitter as you was running 2% faster than normal, does not sound much, but it almost always crashed on the main blitter test. I tried delaying signals like DTACK a bit more, and it did seem to help. Though I put back the original code, and the machine was running for almost an hour without crashing.. So the fault was very intermittent but could happen anywhere in a few seconds of turning on the machine to almost an hour later, or not at all.
After scoping around, each time the scope was placed on the ROM CE signal, it instantly crashed. So there was something obviously wrong this signal somehow. I tried adding a pull-up resistor as I was thinking the load of the scope was too much for the CE line, this again did seem to work but was not conclusive, but the ROM speed dropped back down to 309%
so clearly this was not direction to go in.
So I added in a series of resistor into the CE line (100R currently) and so far the machine seems stable and I can connect the scope probe now the side of the resistor without crashing. So I took some screenshots of the before and after signals...
So I think there is definitely some sort of loading or noise issue on the CE signal. I did try adding in a 22pF capacitor, but this did not change anything, so I added in a second one for 44pF and the machine did not even boot, the corrupt screen. So possible the capacitance of the GAL and ROM IC is simply too much for the STE logic to drive correctly. BOf course there looks to be approximately 1V of undershoot on the signal, could actually latch up CMOS inputs.. So I do need to read up on that again..
So I plan to make some small changes to the DUALTOS boards. Where I will run the ROM CE from the STE CE signal via a ( likely) 100R resistor. Then run the booster CE signal via a second 100R resistor. This way any interference between the GAL and ROM is reduced rather than driving them from the same resistor. Plus the overall load on the STE CE reduced considerably. So I will need to do a revised PCB (again
The ROM PDF says..
Maximum voltage is -0.6V DC, which may undershoot to -2.0V for pulses of less than 20ns. Maximum output pin voltage is VCC + 0.75V DC, which may overshoot to +7.0V for pulses of less than 20ns.
The GAL PDF says..
GAL22V10 devices are designed with an on-board charge pump to negatively bias the substrate. The negative bias is of sufficient magnitude to prevent input undershoots from causing the circuitry to latch. Additionally, outputs are designed with n-channel pullups instead of the traditional p-channel pullups to eliminate any possibility of SCR induced latching.
So the GAL are pretty hardcore by the sounds of it! So it must be the ROM having issues. Which makes sense as I had trouble getting the dualtos board on its own to run stable on this machine.
The machine under test is still running.. I have my scope sampling over each second, and undershoot max is 400mV.. So under the 600mV limit easily. So looking like another mystery solved