My summer project: A colour Stacy

General discussions or ideas about hardware.
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derkom
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Re: My summer project: A colour Stacy

Post by derkom » Mon Aug 03, 2020 8:36 am

I haven't had any more time yet to play with this switching setup, although I do notice that the mux wiring that I built is identical to the mux wiring in c't's configuration. The mux IC is very slightly different, but I would imagine inconsequentially.

However, the c't switcher has this at the top:

Screenshot 2020-08-03 at 10.30.03.png
Screenshot 2020-08-03 at 10.30.03.png (71.15 KiB) Viewed 462 times

Does anyone know what is the function of the connected GAL on the PAK board?

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derkom
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Re: My summer project: A colour Stacy

Post by derkom » Mon Aug 03, 2020 8:15 pm

A lesson was learned tonight: Do not accidentally connect BR to +5V when your CPLD is a 3.3V device. :lol:

So, I toasted the Xilinx chip on the TF536. Luckily I bought one spare when buying the chips for the TF cards I'm going to build up myself, so I pulled off the dead one and stuck on a new one, no problems there.

But I think I maybe don't have any hardware that can program it. I've got a TL866II PLUS, a PICKit 3, and a USB Blaster. Can any of these program the Xilinx CPLD, or do I need to acquire yet another programmer?

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Re: My summer project: A colour Stacy

Post by exxos » Mon Aug 03, 2020 8:18 pm

I thought those chips were 5V tolerant ?
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derkom
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Re: My summer project: A colour Stacy

Post by derkom » Mon Aug 03, 2020 8:34 pm

exxos wrote:
Mon Aug 03, 2020 8:18 pm
I thought those chips were 5V tolerant ?
I saw something on the datasheet about being 5V tolerant for programming. Don't know if it is tolerant on the whole bus. (I was wondering about that, though, since obviously it's sitting on a 5V bus, so it seemed strange that putting 5V on BR would be a problem.)

In any case, I did break it. I was using the Stacy internal DMA bus for grounding BR, and mistakenly put it on a +5V pin, which is right next to GND, and the TF quit. I noticed after that that the regulator was running really hot and producing only around 1V on its output, and 3V3 and GND were shorted. I checked the regulator and the accompanying caps and they were fine, so CPLD was the next thing to test. The short went away when I pulled off the old CPLD, and with the new CPLD on, the regulator is back to producing 3.3V.

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PhilC
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Re: My summer project: A colour Stacy

Post by PhilC » Mon Aug 03, 2020 8:36 pm

@derkom you can program them with a raspberry pi but not tried that myself. There's a guide on here somewhere I think?

P.s. hopefully the ram has survived too.
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derkom
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Re: My summer project: A colour Stacy

Post by derkom » Mon Aug 03, 2020 8:48 pm

PhilC wrote:
Mon Aug 03, 2020 8:36 pm
@derkom you can program them with a raspberry pi but not tried that myself. There's a guide on here somewhere I think?
I see a couple of those projects (OpenOCD, xc3sprog), but it looks like I'll still need a cable I don't own.
P.s. hopefully the ram has survived too.
Indeed, although I do have the chips for my other boards if need be.

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Re: My summer project: A colour Stacy

Post by czietz » Mon Aug 03, 2020 8:57 pm

derkom wrote:
Mon Aug 03, 2020 8:36 am
Does anyone know what is the function of the connected GAL on the PAK board?
It's described in the c't article that was posted: it drives /AS, /LDS, /UDS and /VMA on the PAK. The additional gate makes these output go high-Z.

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derkom
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Re: My summer project: A colour Stacy

Post by derkom » Mon Aug 03, 2020 8:58 pm

czietz wrote:
Mon Aug 03, 2020 8:57 pm
It's described in the c't article that was posted: it drives /AS, /LDS, /UDS and /VMA on the PAK. The additional gate makes these output go high-Z.
Ah, thanks. I missed that in the article.

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derkom
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Re: My summer project: A colour Stacy

Post by derkom » Mon Aug 03, 2020 9:38 pm

I see that I can get a proper Xilinx programmer for not too much, but of course that won't help me tonight. :D Probably a good idea to have one anyway, for firmware updates, etc.

I'm running right up to my summer holiday, so I'm afraid all of this is about to go on hold for a couple of weeks anyway, and then I'll get ahold of the Xilinx programmer and pick up where I left off.

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derkom
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Re: My summer project: A colour Stacy

Post by derkom » Tue Aug 04, 2020 10:56 am

Okay this turned out to be a lot easier than I thought, once I was directed to the right information. I've got the firmware on the new CPLD and the TF once again boots. I can't easily check the RAM at the moment, but will figure that part out eventually.

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