BLITTER RE-CREATION THOUGHTS

Progress on our FPGA cores.
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dhedberg
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Re: BLITTER RE-CREATION THOUGHTS

Post by dhedberg »

Cyprian wrote: Thu Apr 19, 2018 1:38 pm Would be cool to add one feature - hardware C2P conversion.
Like that idea! Would be really nice to have! Too bad it wasn't in there from the beginning! :-(
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exxos
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Re: BLITTER RE-CREATION THOUGHTS

Post by exxos »

Cyprian wrote: Thu Apr 19, 2018 1:38 pm BLiTTER in FPGA? Really cool idea, I second that.

Would be cool to add one feature - hardware C2P conversion.
Now, a standard C2P - chunky160x100 to 4-bitplane 320x200 can take up to 480 000 cycles. With 160 000 cycles per frame it is 3 frames. With the BLiTTER speed it could take advantage of copy speed - 40KB per frame (In this case C2P frame has 32KB)
Doesn't mean much to me.. but if you can explain it all in detail maybe I can get wolfgang to code it into the core..
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Smonson
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Re: BLITTER RE-CREATION THOUGHTS

Post by Smonson »

exxos wrote: Thu Apr 19, 2018 11:23 am I went for the cheapest 3.3V one which would work. No use going for a larger more expensive device.
I actually know so little about FPGAs... That's the cheapest one I've ever seen! Well outside silly devices without about 20 LEs that hardly seem worth the effort.
Stimpy
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Re: BLITTER RE-CREATION THOUGHTS

Post by Stimpy »

Here is some builds in Quartus for some of the Suska parts, thought they are quite interesting numbers.

Cyclone 10LP (10CL055YF484C6G)
55856 Logic Elements

68000 18.86MHz 10143LE (18%)
Blitter 69.45MHz 1403LE (3%)
DMA 197.67MHz 518LE (<1%)
Glue 218.58MHz 591LE (1%)
MMU(DRAM) 141.56MHz 666LE (1%)
Shifter 134.1MHz 1043LE (2%)
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exxos
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Re: BLITTER RE-CREATION THOUGHTS

Post by exxos »

Little bit of headroom there then :)
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Re: BLITTER RE-CREATION THOUGHTS

Post by Stimpy »

exxos wrote: Wed May 02, 2018 10:40 am Little bit of headroom there then :)
Sure, I wanted to just see what it required without the placer breaking a sweat.

Looking at those numbers, especially the FMAX suggest the 68000 would need more time spent on it to improve the delays. Question, is it worth it if the 68000 is still available?

So some prices:

10CL006 ~£7
10CL010 ~£9
10CL016 ~£14
10CL025 ~£19
10CL040 ~£31
10CL055 ~£44

So forgetting the 68000 the 10CL010 would be a good device, probably still only 40% utilised LE.
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Re: BLITTER RE-CREATION THOUGHTS

Post by exxos »

I wonder if someone could try and compile this with a Xlinix device ? If it works and it can run with 5V tolerant IO.. then those devices may be also a option to explore...
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Re: BLITTER RE-CREATION THOUGHTS

Post by Stimpy »

My thoughts were actually a Lattice FPGA might be good. They seem to be cheaper than the Altera / Xilinx parts and of course, Lattice parts have been used in Atari's before!

5V tolerant (from memory) means it will accept a 5V input but you can't drive 5v out. It will drive 3.3v but I don't know how the ST would cope with that....really everyone is ditiching 5v or has ditched last millennium so the best way to deal with that is experiment with some transparent bus transceivers.
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Re: BLITTER RE-CREATION THOUGHTS

Post by exxos »

I was looking towards not using bus transceivers for level translation as it takes up a lot of space on the board.. If I were to do that these blitters could not be used in other machines.. The PCB would probably be too large.

As xilinix has 5 V tolerant I/O I would not need transceivers. I did not consider any other chips I don't know anyone that uses Lattice. Of course I really want to use Atmel, simply because their stuff is simple and I am used to it. I really want to avoid spending time learning the new chip if possible. Though as everything is wired up for Altera.. That would be a better choice to use, but I cannot remember if it has 5V tolerant I/O.

As I am working with real hardware I would prefer to use 3.3V stuff interfacing to 5V levels. There is already complete machine rebuilds like Suska which run on 1.8V or so. I am not looking to recreate that. I'm looking towards creating compatible replacement chips. I really do not care what what mainstream is doing with voltages. We are retro people, it's all 5V stuff!
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Stimpy
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Re: BLITTER RE-CREATION THOUGHTS

Post by Stimpy »

Lattice are a pretty big company....and if you're not using anything specific to the FPGA then VHDL is pretty portable. The Suska code seemed very portable, I used Xilinx and pretty sure it built in the LAttice tools too.

So is the ST happy with 3.3v logic levels? I thought the ST (all all the different versions and revisions) have pretty flaky buses, putting 3.3v logic into the mix could cause even more problems?!

Unless you are happy buying old stock (grey market / dubious suppliers etc), 5V stuff is gone. Bus transceivers are the only way forward to interface to older logic.
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