RTC + BOOSTER THOUGHTS

[exxos]

I designed the RTC for the falcon here https://www.exxosforum.co.uk/atari/store2/#0089 though no reason why this cannot be mashed into the current V2.5 booster design.

It could probably use the same address ranges as the falcon (or not). Though I have the booster PLD connected to the address bus fully anyway. There are a few spare IO pins, so I can run chip enable to the RTC chip.

While I can add this to the next prototype, I really could do with someone to write the software for this. There never seems to be a "good" RTC program for the falcon. Though I think a new program which can list all the address ranges and edit everything, or reset everything would be ideal.

It is also my intention to store booster settings in the NVRAM, part of the software control. So booster can be turned on or off via software and settings can be stored in the NVRAM. This way TOS selection can also be stored, so boot up can use TOS104 or TOS206 for example.

[exxos]

Looking at the http://pdfserv.maximintegrated.com/en/d ... 2C887A.pdf DS12885, it has AS and DS, and a single 8 bit IO. So assuming here, to use AS to set the RTC address, and use maybe LDS to set data to the RTC. Though I am a little confused over AS, DS, and read/write here.

rtc.JPG (70.43 KiB) Viewed 2689 times

It says..

Multiplexed, Bidirectional Address/Data Bus.
The addresses are presented during the first portion of the bus cycle and latched into the device by the falling edge of AS. Write data is latched by the falling edge of DS (Motorola timing) or the rising edge of R/W (Intel timing). In a read cycle, the device outputs data during the latter portion of DS (DS and R/W high for Motorola timing, DS low and R/W high for Intel timing). The read cycle is terminated and the bus returns to a high impedance state as DS transitions low in the case of Motorola timing or as DS transitions high in the case of Intel timing.

Address Strobe Input.
A positive-going address-strobe pulse serves to demultiplex the bus. The falling edge of AS causes the address to be latched within the device. The next rising edge that occurs on the AS bus clears the address regardless of whether CS is asserted. An address strobe must
immediately precede each write or read access. If a write or read is performed with CS deasserted, another address strobe must be performed prior to a read or write access with CS asserted.



So /AS programs the address, but then when reading data for example, we have to set DS, but is /AS still low at that point or not ?!

[rubber_jonnie]

If I recall, the Areal RTC software allows you to choose the memory location, I've attached it here so you can play

Attached a few other bits and bobs too.