Put 2 YM2149 into the ST

[exxos]

Hmm does the SND_CS output depend on the LDS abd UDS signals from the CPU?

I have no idea.. it would have to be tried on real hardware to see if GLUE allows the full 16bit access. Though your idea seems to make a logical way to go about it all.

[Gunstick]

Meanwhile my logic simulator is half-fully featured.
But it bugs a bit, because I tried to use a bidirectional data bus in a software which does not like stuff like that.
So the "read data" operation, which is rarely used, is disabled. I just deleted those connections (was a kludge anyway)

https://circuitverse.org/simulator/embed/33301

One thing which I expected is that due to timing issues, selecting a register in YM0 will also select the same register in YM1 if that's the moment you switch between the 2 chips. But then the data written goes to the correct one. So the register selection is a glitch which should not disturb the normal operation.
In case circuitverse goes bust, copies of the design as pictures:

Screenshot_2019-10-30_01-48-06.png (125.97 KiB) Viewed 4138 times

The ym2149 simulating just the registers. Dout8 was the trial to get data read working in this simulation, but was not possible.

Screenshot_2019-10-30_01-49-55.png (52.47 KiB) Viewed 4138 times

[Gunstick]

Edit But after reading Gunstick's method of latching bit 4 of the data written to register select (ie. D12 when BDIR is write and the address is $FFF8800) sounds awesome to me.
Extending that to latching D12,D13,D14, and D15 would allow in theory up to 16 YM chips on the same address space(!!)
(That's 48 chanels of audio and 256 GPIO pins)

I thought about that. Idea would have been a PCB which you could stack as many as you want and address would be just the next one.
But this needs more circuitry.
And how do you want to fit a stack of 16 chips in the ST case?
What use to make of the new GPIO?
Some idea would be to have R2R digital to analog converters on there. One channel on the printer port (register 0F), the other channel on the new register 1F. And the other gpio would be used to control some stuff like: switch 0F into printer or into DA converter. Connect channels A-C like Atari did or like the real design should be. Mix YM0 left and YM1 right, or mix Channels A&D left, C&F right. I surely will find more ideas to use all pins for some usage. 2 more floppies?

[keli]

Reading the data sheet for the AY-8910, it seems that General Instrument had a similar scheme in mind:

The four low order address bits select one of the 16 registers (R0-R17(base 8)). The six* high order address bits function as "chip selects" to control the tri-state bidirectional buffers (when the high order address bits are "incorrect", the bidirectional buffers are foreced to a high impedance state). High order address bits /A9 and A8 are fixed in the PSG design to recognize a 01 codel high order address bits DA7-DA4 may be mask-programmed to any 4-bit code by a special order factory mask modification. Unless otherwise specified, address bits DA7-DA4 are programmed to recognize only a 0000 code.

Note the sentence I highlited in bold. This means that we have to force DA7-DA4 to zero when accessing the "register select" of any additional YM chips, otherwise it will not recognize the register access as belonging to it. (Unless we're so lucky to have found one that has been mask programmed to recognize a different high order address, which is unlikekly, but then it could be piggibacked on top of the existing YM chip without any additional logic.)

*) The A8 and /A9 pins are also a part of the address decoding, but probably only relevant for designs using General Instrument's own CP1610 processor**.
**) Note that the CP1610 processors seem to have had an interleaved address/data bus, in which case programming the PSG on such a processor would have shown the registers directly as memory mapped registers at address range $100-$10F and not the indirect method on the Atari ST.

Edit: The data sheet for the YM2149 simply states that DA7-DA4 must be 0000 when selecting a register, (as they probalby never produced custom YM2149s with a different "high order address bits".)

[Gunstick]

Hi

interesting if the high address bits are not 0 that the YM does not give any data. So I tested this on real hardware, and indeed, I cannot read back a value written if the bit 4 is set. Also hatari emulates this correctly. I read back 255
And trying to write does not work (the previeous register contents is preserved).
So, well that means that my simple circuit will not work, and I need a bit of redesigning.

Thanks for this info!

[keli]

Due to the YM going high-impedance when the register address is not correct, the circuit can be much simpler.

1. Leave the original YM (YM0) connected as-is
2. Invert bit 4 on YM1 when BDIR and BC1 are both 1,
3. Connect DA0-3, DA5-7, BDIR, BC1-2, A8, ~A9, etc of YM1 to the same pins as YM0. (the GPIO and analog outputs must go somewhere else of course)

The second part is a bit more difficult than just saying it, as the bit must not be inverted when writing or reading data... and it must not interfere with the bidirectional nature. I solved this by using 3-state buffers and inverters:

dual_ym_4.png (33.46 KiB) Viewed 4080 times

Edit: Replaced the schematic with a fixed one after discovering an error in the BDIR/BC1 decoding

[keli]

.... and before I go to bed, here's a solution that uses a 2 to 4 decoder (with inverted outputs) instead of a bunch of nand gates to decode the bus control signals:

dual_ym_alt.png (25.29 KiB) Viewed 4075 times

[Gunstick]

Nice, thanks.
You are well better in circuitry than me.

That online simulator does really not like tri-state bus setups.
No idea if it works for you:
https://circuitverse.org/simulator/embed/34126

Don't you need to memorize which chip got selected (i.e. having that latch somewhere) so when you do register write, the data goes to the correct chip? Or is a bus buffer also memorizing previous state?

Modified my original circuit which seems to work as it should. It has not the best circuity, LOL. That's for another day.
https://circuitverse.org/simulator/embed/33301

[keli]

Don't you need to memorize which chip got selected (i.e. having that latch somewhere) so when you do register write, the data goes to the correct chip? Or is a bus buffer also memorizing previous state?

All 8 address bits are latched inside the YM, so there is no need to store them externally. The chip unselects itself when A7-A4 is not 0000, which is exactly what we want (after cheating it to think the 4th address bit is the inverse of the actual value.)

[keli]

Don't you need to memorize which chip got selected (i.e. having that latch somewhere) so when you do register write, the data goes to the correct chip? Or is a bus buffer also memorizing previous state?

All 8 address bits are latched inside the YM, so there is no need to store them externally. The chip unselects itself when A7-A4 is not 0000, which is exactly what we want (after cheating it to think the 4th address bit is the inverse of the actual value.)

Actually you were right. The buffer that gets enabled on data read needs to be enabled only if the register address bit was set to 1 previously.

A solution could be to replace the two (non-inverting) buffers with an analog switch such as a 74x4066.