Put 2 YM2149 into the ST

[Gunstick]

Hi

I was wondering if it's possible to double the YM soundchip.
Not knowing exactly how the adress decoding is done by Atari, either one could simulate new YM registers from $10 to $1F, or create a second YM in the address space (but then you get battles with the MMU, especially in recent machines where the shadow registers have gone).

Has anyone given some thoughts about this idea?

Having new registers or another address for the chip has the advantage of easier programming than to use another method (like plugging it into the rom port, or on a midi channel ...)

Gunstick/ULM

[exxos]

You can pretty much put anything on the bus you want at any (unused) address. Though of course you will need custom software to talk to the hardware.

[Gunstick]

Ah, that's interesting. Also on falcon who does bus errors outside of the official YM addresses?

As, for some unknown reason, there was never a dual YM done, it would be good to define how it should be connected so that software always knows where to find the chip.
Best if can be piggybacked on top of the original with cutting the least amount of pins.
Also then there will be an additional 16 GPIO ports inside the ST.

[exxos]

On the ST the GLUE issues bus error after a lot of clocks, I forget the number , maybe 128.

[Gunstick]

I tried to figure out how the YM is interfaced to the ST bus. Checked the original Atari documents and some of the STremake posts. But I could not figure out where BC1 and BDIR are connected to, and how they are used when accessing the YM.

[exxos]

They are driven via a LS02, from SND_CS (GLUE) , RW (CPU), A1 (CPU)

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[Gunstick]

Hi

I'm no circuit designer, so no idea if this would work or if it would glitch the latching of register numbers into both YMs.

I put it into this online simulator https://circuitverse.org/users/11547/projects/33301

Screenshot_2019-10-26_21-39-58.png (34.91 KiB) Viewed 5146 times

[exxos]

I'm not really sure what your trying to do there ? But you would need to read up on the YM chip, how to program its registers and access it etc, and build a address decoder for it and assign it a register to talk to it like the current YM is accessed.

The ST memory map pdf will show what address SND_CS is driven (by glue) so you need to ( I assume free space somewhere around the same registers) and just map the new YM chip to free IO space. Then you generate a new SND_CS and use the same YM circuit.

[Gunstick]

I tried to put the 2nd YM into the same space as the current YM (so on ff8800 and ff8802), but have some additional logic to emulate new registers.
So you effectively obtain a "new" YM chip with 32 registers.

To address the second YM, I tap on bit 4 of the register address (which is usually 0 as the YM only has registers 0-15).
So if you address register 16, bit 4 becomes 1 and so the YM selection pins (BC1 & BDIR) become active on the second YM, which then stays active (due to the Dlatch) until a new register for the original YM is selected.

Result is that R0/R1 is the frequency of channel A ($00 / $01) and the envelope is on R13 ($0D) as usual
And that R16/R17 is the frequency of the 'new' channel D ($10 /$11) and it's envelope on R29 ($1D)

[keli]

They are driven via a LS02, from SND_CS (GLUE) , RW (CPU), A1 (CPU)


Capture.JPG

Hmm does the SND_CS output depend on the LDS abd UDS signals from the CPU? If not, could these be combined with SND_CS to put the second YM chip on the odd byte of the same address (Wen LDS is active).

So the address map would become:

Address	size	chip	function
$FF8800	byte	Primary YM	Read data/Register select
$FF8801	byte	Secondary YM	Read data/Register select
$FF8802	byte	Primary YM	Write data
$FF8803	byte	Secondary YM	Write data

Edit But after reading Gunstick's method of latching bit 4 of the data written to register select (ie. D12 when BDIR is write and the address is $FFF8800) sounds awesome to me.
Extending that to latching D12,D13,D14, and D15 would allow in theory up to 16 YM chips on the same address space(!!)
(That's 48 chanels of audio and 256 GPIO pins)