ST SHIFTER operation ?

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exxos
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ST SHIFTER operation ?

Post by exxos » Sun Oct 15, 2017 1:04 pm

Does anyone know exactly how and what the ST shifter is actually doing ?

I mean we have RGB data in RAM, which load LOADed into the shifter, where it outputs the data to the RGB drivers. Is that pretty much just a "straight in and out" type thing ?

I'm assuming the shifter must load in 16 pixels worth of data at a time. So would need 16 MMU > shifter reads to do this ? Where the shifter will "shift" the data based on the speed of the "dot clock" (originating from the master 32mhz clock).

Of course there is 5 address lines in there, assume to program the bis for what resolution is being used.

I'm really thinking could we just re-do the shifter in a modern PLD. AFAIK the shifter isn't really doing that much , so if we know exactly how its working then no reason we can't emulate it and even improve on it.
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keli
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Re: ST SHIFTER operation ?

Post by keli » Sun Oct 15, 2017 3:00 pm

It also has to map the palette index for each pixel to the rgb values stored in the palette registers. I assume the 5 address lines are also for updating the palette registers.

16 palette entries require four address lines just for addressing them. (Mapped via FF8240-FF825E, or 0xxxx) The resolution is set via FF8260 and it looks like that's the only valid combination with the fifth address line set on the STF blitter (ie 10000), the STE blittter adds the hard scroll register at FF8265 (ie the low byte at FF8264)

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Re: ST SHIFTER operation ?

Post by exxos » Sun Oct 15, 2017 5:32 pm

OK, so we have 16 palette registers and resolution register. Though what is the decision to output the data to the RGB ports or store values in a register? One address range must be to latch the video data, others for palette data.

So 5 data lines is 32 possible address..

I'm no expert on file formats or video data etc, though assume the format is like FF would output 2 pixels with palette colour 15 ? and 00 would be palette colour 0 for 2 pixels..

In which case, it doesn't sound complicated to replicate the shifter logic. We just program the palette registers, then the video data coming in just needs to act as chip select lines for the registers, then the palette data gets output as RGB data.. Probably would need to draw this out, but sounds easy in my head anyway :lol:
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Re: ST SHIFTER operation ?

Post by keli » Sun Oct 15, 2017 6:26 pm

exxos wrote:
Sun Oct 15, 2017 5:32 pm
OK, so we have 16 palette registers and resolution register. Though what is the decision to output the data to the RGB ports or store values in a register? One address range must be to latch the video data, others for palette data.
As far as I understand, the video data are latched when the /LOAD is driven low -- the address pins are not used at all in that case.

The registers are accessed by driving a register address on the address pins and pulling /CS low and setting R/W according to whether it's a read (high) or a write (low) operation.
exxos wrote:
Sun Oct 15, 2017 5:32 pm
So 5 data lines is 32 possible address..
It only uses 17 of them 0xxxx for the palette registers and 10000 for the graphics mode.
exxos wrote:
Sun Oct 15, 2017 5:32 pm
I'm no expert on file formats or video data etc, though assume the format is like FF would output 2 pixels with palette colour 15 ? and 00 would be palette colour 0 for 2 pixels..
It's a bit more complicated than that. Video memory is organized in bit planes with each word of memory representing 16 pixels in a single plane.
So in order to be able to show pixel data in low res (4 bit planes), the Shifter needs to latch four words of image data. Stored in a 64 bit shift register I assume, possibly explaining why it's called the Shifter ;) To generate a single pixel, the Shifter combines a single bit from each word and uses these to look up the color value in the palette.

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Re: ST SHIFTER operation ?

Post by troed » Sun Oct 15, 2017 9:48 pm

1) Read Alien's description on how the Shifter works in Alive 11:

http://alive.atari.org/alive11/oscan2b.php

2) Read everything Ijor has written on A-F on the subject - esp. since he's decapped a Shifter and looked at the actual logic :) (Several different threads over the years)

If we want a re-implementation to be "demo compatible" there are a lot of intricate timings to take care of.

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Re: ST SHIFTER operation ?

Post by exxos » Sun Oct 15, 2017 10:19 pm

Thanks, will have a read tomorrow when more awake.

I kinda lost respect for Ijor a while ago when he made a fundamental mistake of using a LA to check on clock syncs. I said there were all perfectly in sync and I pointed this out to him , and he shot me down pretty much and carried on. See here. Though to be fair he did apologize later and say I was right in what I said. Absolutely nobody even questioned this, or even took my "view" on things, typical of people on AF of course. I gave up reading anything after that, pretty much with the whole forum.

Anyway, I think people here are more motivated to actually do physical work and get things done. IMHO we have the right set of people here to create some good hardware :)
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Re: ST SHIFTER operation ?

Post by exxos » Sun Oct 15, 2017 10:39 pm

keli wrote:
Sun Oct 15, 2017 6:26 pm
It's a bit more complicated than that. Video memory is organized in bit planes with each word of memory representing 16 pixels in a single plane.
So in order to be able to show pixel data in low res (4 bit planes), the Shifter needs to latch four words of image data. Stored in a 64 bit shift register I assume, possibly explaining why it's called the Shifter ;) To generate a single pixel, the Shifter combines a single bit from each word and uses these to look up the color value in the palette.
OK, so we need 4x 16bit shifters. Assume this 16bit data is read consecutively from RAM ? Such as , 16bit plane 1, then 16bit plane2.. etc

That would indeed greatly complicate things :roll:
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keli
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Re: ST SHIFTER operation ?

Post by keli » Mon Oct 16, 2017 8:03 am

exxos wrote:
Sun Oct 15, 2017 10:39 pm
OK, so we need 4x 16bit shifters. Assume this 16bit data is read consecutively from RAM ? Such as , 16bit plane 1, then 16bit plane2.. etc

That would indeed greatly complicate things :roll:
You'd probably need 8 of them. 4 for the data currently being loaded from memory and the other 4 for the data being shifted out to the screen.

But yes the bit planes are interleaved in memory so the blittter will always get one word from alternate bit planes on every load.

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Re: ST SHIFTER operation ?

Post by exxos » Mon Oct 16, 2017 9:49 am

keli wrote:
Mon Oct 16, 2017 8:03 am
You'd probably need 8 of them. 4 for the data currently being loaded from memory and the other 4 for the data being shifted out to the screen.
Possible yes. I was thinking with a 64bit shifter register, that 16bits would get shifted out, then the top bank of 16bits (which would have been shifter to bank 2 and now empty) would then get loaded.
keli wrote:
Mon Oct 16, 2017 8:03 am
But yes the bit planes are interleaved in memory so the blittter will always get one word from alternate bit planes on every load.
OK, so I'm not sure how planes work. Which bit of data in memory actually goes into RGB data output ?

If we had 4 banks of 16 shift registers, then that becomes parallel in, serial out. So bit 0 of each 16bit bank would be output somewhere first...
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Re: ST SHIFTER operation ?

Post by rpineau » Mon Oct 16, 2017 3:08 pm

Here is an quick diagram of how the 4 bit plane mode works on the ST :
http://perso.numericable.fr/~ckckck/Ami ... igure2.JPG

Rodolphe

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