Yep. They are all verilog inputs, passed directly to the shifter module.
I guess the next most logical failure mode for this scenario is that R/W is not being driven high enough to be buffered by the '245s on the FPGA board (we have seen Icky's CS and it looks good to me).This is expected, but shouldn't be relevant. What really matters is the relation with LATCH, not with CS. And LATCH is deasserted half cycle earlier than CS. Furthermore, even if there would be a hold timing problem, the symptoms should be different. Here seems that the bus is never driven at all on those cycles.
That signal goes straight from the shifter socket, through the ribbon cable, and direct to the input on one of the 5v-tolerant buffers, then to the FPGA pin:
That signal is somewhat noisy on my machine, but when it drives low, it really hits the floor. It originates with the 68000 and has a 4.7K pullup to 5v in the schematics I'm looking at.
Troed or Icky, perhaps you could be kind enough to provide a scope shot of R/W when you have time?