Note that it doesn't exactly seem that D9 is corrupted. It seems that at least on some cycles, the bus (the local Shifter-RAM bus) is not driven at all. If this is true, this could only happen at the level shifter or possibly at the FPGA itself.czietz wrote: ↑Tue Dec 04, 2018 5:51 pmBut iirc Smonson made a test program that generates a trigger signal upon faulty reads. Wouldn't the best way forward be to use that test program and to probe (with a scope) e.g. D9 at every buffer, level shifter or latch it passes through. Somewhere it must get corrupted.
Probing D9 at the FPGA side on a "bad" read might be interesting. But unless the scope can probe two signals and trigger on a third one, then it might be difficult to match the D9 signal with the Shifter access.