Here's my current project that's been keeping me up late for several months.
I'm creating a HDMI/DVI video out for my STFM by interfacing a Cyclone-II FPGA with the shifter socket. The lowest-spec Cyclone-II is cheap and can directly drive an HDMI/DVI video signal. It also has onboard SRAM which I will use to implement scanline doubling. The benefits of this as opposed to an external upscaler are:
- Perfect picture clarity - no analogue signal paths at any point
- No buffering delay (in mono - one scanline delay in colour)
- Can display 50Hz natively on any PAL TV, just like in the good old days
- Should work with normal videomodes as borderless 640x400, or in overscan modes, automatically switch to another video mode such as 720x480 (*in theory).
The FPGA is clocked at 32MHz and feeds a 16MHz clock into the Atari through the shifter's clock out pin.
The video frames are synchronised with the ST's DE signal (the first DE after a gap of greater than 2048 clocks equals the start of a new video frame).
Shifter data is loaded into the FPGA the same way as the original shifter (through 5-to-3.3v level converters) on the LOAD pulse and then shifted out into a scanline buffer in FPGA RAM. After a one-scanline delay, that data is then clocked out to the DVI connector. The purpose of the delay is to implement the scanline doubler for colour modes.
The reason why the desktop looks weird in that pic is that I have my stripboard prototype set up with only writeable shifter registers, it won't drive the bus to read them back. So the ST is confused about what resolution it's in.
The biggest obstacle that I'm dealing with right now is instability. In monochrome, the whole system is reasonably stable, but in colour (50Hz in my case) the length of the video frames are not steady - some are shorter, some are longer. I am working off the theory that this is because of noise in the clock. There is a lot of noise all over the whole circuit actually. Tomorrow I'll receive the first manufactured PCBs with a good ground plane underneath everything, and a buffer on the clock right before it goes into the shifter socket. I hope that will resolve the instability issue... I'll let you know how it goes.