Alt-RAM logic brain fart

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Badwolf
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Re: Alt-RAM logic brain fart

Post by Badwolf » Sun Oct 04, 2020 10:01 pm

ctirad wrote:
Sun Oct 04, 2020 8:57 pm
Badwolf wrote:
Sun Oct 04, 2020 6:53 pm
* More memory. This was the main aim of this project. Memory, and lots of it. DRAM is the only real option here. This will again need 3.3V infrastructure and probably a bigger CPLD.
I'd use SDRAM. You can get 128MB or more for cheap. Directly soldered. The controller should fit into something like XC95144XL as on CT6x cards or ACA cards from Jens. Or similar CPLD from Altera/Intel. These devices are still 5V tolerant.
Yeah, Xilinx still does 5V chips, but I don't think Altera/Intel do any more. Would need to switch ecosystem. Not sure how much is involved with that.

Let's think. If I routed all the data and address lines via the CPLD I wouldn't need level shifting, but that'd need around 114 pins! Routeing address only would need around 50 (give or take), then only level shifters for the data lines. That sounds doable, and is, I suspect, what the TF536 does.

Does Xilinx programming require specific Xilinx-compatible hardware?
What about some (quad)SPI expansion port for fast interfacing with some MCU based daughterboard, that would serve as gateway to USB, Ethernet, Wifi, etc..?
Ha! Crawl before I can sprint, I think. ;-)

One of my main aims is to keep the form factor small enough that the PSU can remain in place on the Falcon, so concentrating on the core goal of memory at the moment. The acceleration is a nice side effect. Programmable ROM would be nice, but anything else I can piggyback on later would be purely bonus. :-)

Thanks,

BW.

Badwolf
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Re: Alt-RAM logic brain fart

Post by Badwolf » Sun Oct 04, 2020 10:08 pm

exxos wrote:
Sun Oct 04, 2020 9:49 pm
If its being hooked to the CPU bus, it already has a pull up on the 5V side.
viewtopic.php?f=80&t=79&p=16229#p16229
Interesting, ta.

Although my A31:24 and D15:0 don't have pull-ups. Oops. Are they meant to? :oops:

BW

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Re: Alt-RAM logic brain fart

Post by exxos » Sun Oct 04, 2020 10:13 pm

Badwolf wrote:
Sun Oct 04, 2020 10:08 pm
Although my A31:24 and D15:0 don't have pull-ups. Oops. Are they meant to? :oops:
You would have to check the schematics to see if there is any on the bus on those pins or not..
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Badwolf
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Re: Alt-RAM logic brain fart

Post by Badwolf » Sun Oct 04, 2020 10:20 pm

exxos wrote:
Sun Oct 04, 2020 10:13 pm
Badwolf wrote:
Sun Oct 04, 2020 10:08 pm
Although my A31:24 and D15:0 don't have pull-ups. Oops. Are they meant to? :oops:
You would have to check the schematics to see if there is any on the bus on those pins or not..
On the Falcon they're NC & floating, but that's as they're genuinely never used. I'll have to dig back into the 030 manual to see if they're meant to be tied up. I might have just been lucky with my AltRAM address lines!

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Re: Alt-RAM logic brain fart

Post by exxos » Sun Oct 04, 2020 10:23 pm

Badwolf wrote:
Sun Oct 04, 2020 10:20 pm
On the Falcon they're NC & floating, but that's as they're genuinely never used. I'll have to dig back into the 030 manual to see if they're meant to be tied up. I might have just been lucky with my AltRAM address lines!

I always go with the logic, unintended, but never leaving anything floating used or not... But with Atari cost-cutting all the time they probably never connected pullups on the unused CPU pins...

But yeah, you should really have pullups on those pins which haven't on the motherboard..
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Badwolf
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Re: Alt-RAM logic brain fart

Post by Badwolf » Sun Oct 04, 2020 10:28 pm

exxos wrote:
Sun Oct 04, 2020 10:23 pm
But yeah, you should really have pullups on those pins which haven't on the motherboard..
Left a note to myself :blonde:
Screenshot 2020-10-04 at 22.25.46.png
Screenshot 2020-10-04 at 22.25.46.png (165.67 KiB) Viewed 483 times
:lol:

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Re: Alt-RAM logic brain fart

Post by exxos » Sun Oct 04, 2020 10:29 pm

Badwolf wrote:
Sun Oct 04, 2020 10:28 pm
Left a note to myself :blonde:
:bravo: :blonde: :lolbig: :clown:
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ctirad
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Re: Alt-RAM logic brain fart

Post by ctirad » Sun Oct 04, 2020 11:41 pm

Badwolf wrote:
Sun Oct 04, 2020 10:01 pm
Let's think. If I routed all the data and address lines via the CPLD I wouldn't need level shifting, but that'd need around 114 pins! Routeing address only would need around 50 (give or take), then only level shifters for the data lines. That sounds doable, and is, I suspect, what the TF536 does.
It seems so. Although I would rather split the design into two cheap CPLDs, instead of a single expensive one. One for SDRAM and other for the Falcon interfacing, flash ROM, expansion port... The CT6x schematics is definitly a good source to studiyng, although 68060 is 3.3V device, so the level shifitng is done elsewehere.
With a memory soldered onboard and 4 layer PCB you should still be able to keep the board footprint reasonbly small.

Alternatively, you can use 72pin SIMM (or two) to make things much simpler. In that case the sockets will be most probably more expensive than RAM ;)
Does Xilinx programming require specific Xilinx-compatible hardware?
You only need a jtag cable. You can get either original one or one of many clones.
There are also some alternative solutions like xc3prog, that can use a generic FTDI based jtag or some DIY solutions that connets to LPT port.

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