MNT VA2000 graphics card in a Mega ST
Posted: Mon Nov 20, 2017 5:28 pm
I recently found this open source FPGA graphics card made for the Amiga ZORRO II/III expansion bus. After studying the inner workings of the ZORRO II expansion bus, I noticed it was pretty close to the bare m68000 CPU bus.
Feeling brave, I ordered a card from his web shop and now I have a shiny Spartan 6 based card in a nice little cardboard box lying on my desktop.
After studying the Verilog source, I realized creating a fully compatible Zorro adapter is out of my reach, but probably also an overkill, as due to the openness of the firmware, I can just change the firmware to talk directly to the CPU bus. This means I only need a physical adapter from the 100 pin Zorro II card edge connector to the 64 pin DIN type B connector on the Mega ST motherboard.
There was a slight hitch with the /DTACK pin on the VA2000. The level converter it is wired through is set to always drive the pin, whereas on the 68k bus it must be an open collector. I think I solved it by connecting the pin to the enable pin on a 74125 buffer, with it's input wired to GND and output to the expansion pin. Here's the final schematic showing the almost 1-1 wiring. Extra pins I won't be using, I wired to a pin header, useful for some future experiments:
... and the PCB ended up looking like this:
Now I just need to get a prototype pcb ordered, solder everything together, and rewrite the FPGA firmware. Piece of cake, eh?
Feeling brave, I ordered a card from his web shop and now I have a shiny Spartan 6 based card in a nice little cardboard box lying on my desktop.
After studying the Verilog source, I realized creating a fully compatible Zorro adapter is out of my reach, but probably also an overkill, as due to the openness of the firmware, I can just change the firmware to talk directly to the CPU bus. This means I only need a physical adapter from the 100 pin Zorro II card edge connector to the 64 pin DIN type B connector on the Mega ST motherboard.
There was a slight hitch with the /DTACK pin on the VA2000. The level converter it is wired through is set to always drive the pin, whereas on the 68k bus it must be an open collector. I think I solved it by connecting the pin to the enable pin on a 74125 buffer, with it's input wired to GND and output to the expansion pin. Here's the final schematic showing the almost 1-1 wiring. Extra pins I won't be using, I wired to a pin header, useful for some future experiments:
... and the PCB ended up looking like this:
Now I just need to get a prototype pcb ordered, solder everything together, and rewrite the FPGA firmware. Piece of cake, eh?