PLD SDRAM controller ?

[exxos]

Anyone explain how to actually program one ?

I know the @terriblefire stuff has it in, I can't find where I saw the controller now, but didn't think was much to it.. Though with all the code (and stuff on the net) being all VHDL, it doesn't really help as I really want to build a controller in the Atmel PLD's which I am used to in WinCUPL (which is more pure logic functions than C type syntax)

I can't imagine it being much more than a load of counters anyway ?!

[cmorley]

I have done a very low resource one for the A500 trapdoor and a higher resource one in my dev A500 fast RAM/accelerator (thread on this forum).

It's mostly state machine(s) TBH. You need to initialise the RAM & set the mode (sets cas latency and burst mode). Then you need to precharge, activate, read/write and refresh according to the state machine. The ISSI datasheets for SDRAM have a good visual diagram of the state machines for SDRAM - many of the other vendors (e.g. Winbond) just explain it all in words which seems very confusing.

For the A500 fast RAM I bury refresh cycles during 68000 thinking time (AS high) or when the CPU is accessing non-fast RAM. So you don't necessarily need counter(s) for refresh (n per x ms in datasheet).

You can also hold the data value by toggling CKE at the exact right point which means you don't need to latch the data coming out of the SDRAM for a slow non-synchronous bus. Again, see an ISSI datasheet they have this in timing diagrams for easy understanding.

I used verilog for this... I did close timing @96MHz on my super low resource version for a 10ns 7064S (maybe A can't remember off the top of my head) which the 1504AS is a clone of... but I haven't tried it on that chip in meatspace (only Sim).

[Badwolf]

I’ve been working on just this in verilog on and off for the last three of weeks!

Mine’s currently taking a cue from Stephen’s old TF330 sources https://github.com/fluffyfreak/tf330/tree/master/rtl and tweaking it to my chips and circumstance.

It worked right up to the point it didn’t any more and I’m trying to figure out if it’s my logic or the Chinese-acquired silicon on the board.

I did find a couple of other examples on the web, but none using schematic design, I’m afraid.

Like cmorley says, it’s a clocked state machine starting with initialisation steps, then going into idle, handling refresh cycles or read/write cycles depending on demand or, in my case, a counter.

I was falling foul of the synchronisation race at one point, though, so thanks @cmorley for the CE tip. I wasn’t sure that’d work.

The datasheets talk about commands a lot, but it’s not that dissimilar to old style DRAM if you look at what they are: combinations of ras, cas and we for the most part. The initialisation requires you set burst count (can be one), delays etc, but that’s just putting a special address on the line and asserting cas and we, say.

I haven’t got into burst cache filling and all that yet.

BW

[exxos]

ah it might have been in the 330 sources I saw it in before... This is just for a 68K machine, so burst mode and anything else "fancy" just isn't needed anyway.

Will have a look at the ISSI datasheet when I get a mo..

[terriblefire]

ah it might have been in the 330 sources I saw it in before... This is just for a 68K machine, so burst mode and anything else "fancy" just isn't needed anyway.

Will have a look at the ISSI datasheet when I get a mo..

There is the TF sources... officially here..

https://github.com/hologenics

My original SDRAM controller is...

https://github.com/mist-devel/archimede ... /rtl/sdram

SDRAM controller in a PLD may be "fun" as it needs a 10 bit counter.

[exxos]

SDRAM controller in a PLD may be "fun" as it needs a 10 bit counter.

Oddly I was working on a binary counter last week for another project.. Doable at least anyway.

[terriblefire]

Oddly I was working on a binary counter last week for another project.. Doable at least anyway.

Worth a try. We know the XC95144XL chip will do it so consider a shift to that?

[exxos]

Worth a try. We know the XC95144XL chip will do it so consider a shift to that?

Was that the chip on the TF536 ?

Was thinking of trying to use a smaller xilinx chip as does need all the 030 stuff in it etc, but I have no idea how to use that stuff. Did send a message to @agranlund to see if he could port to a smaller device, but doesnt look like hes logged in for the past few weeks.

Anyway, I was just looking to see if I could do it in a Atmel as I use them anyway for stuff.. but for the board I have i mind would only have the chip and a single 16bit SDRAM like this one https://www.mouser.co.uk/ProductDetail/ ... pB7A%3D%3D

I just wanted a small 68K alt-ram board. The ones I built (12+ months ago now) all used SRAM and it cost £100+ just in the RAM.. hence looking to just have a sane solution using SDRAM as its like 100x cheaper!

[terriblefire]

Worth a try. We know the XC95144XL chip will do it so consider a shift to that?

Was that the chip on the TF536 ?

Was thinking of trying to use a smaller xilinx chip as does need all the 030 stuff in it etc, but I have no idea how to use that stuff. Did send a message to @agranlund to see if he could port to a smaller device, but doesnt look like hes logged in for the past few weeks.

Yeah i promised i'd look into doing that for you a while back but... kinda got side tracked.

The TF536 uses the bigger 288 variant. TBH with the 144 pins you can do all of the address mux and control in one... *might* fit in the TQ100 variant. I remember that the XC9572 variant does not have enough pins as some are NC on the 72 vs the 144.

The Xilinx stuff is so nice and easy i just use it everywhere.

[exxos]

Yeah i promised i'd look into doing that for you a while back but... kinda got side tracked.

The TF536 uses the bigger 288 variant. TBH with the 144 pins you can do all of the address mux and control in one... *might* fit in the TQ100 variant. I remember that the XC9572 variant does not have enough pins as some are NC on the 72 vs the 144.

The Xilinx stuff is so nice and easy i just use it everywhere.

If you think a smaller chip wont do, I can probably just port the TF stuff right over..I think that is what you basically suggested a while back anyway.. I need to do the address decoding in the thing, so thats 23 address lines gone right off the bat.