The rev3 version of my Falcon Booster project has been the first board that attempted to include all the features (bar DSP support, which needs more investigation) the project hopes to address.
It's a development board, so it's still not possible to mount it and the stock PSU at the same time, but otherwise it carries a 50MHz external 030 CPU, flash ROM and 32 bit SDRAM.
The first built board has a few bodge wires as rework has lost pins and broken traces and the clock lines are all re-routed as I experimented with inline termination, but it works and works well at 50MHz with 128MB fast, 32-bit AltRAM.
- dfbr3_1_dusty.jpeg (251.48 KiB) Viewed 2184 times
So I tried to build a second board to prove it wasn't a fluke, this time trying to avoid all the bodge wires. This one carried only 32MB AltRAM (much cheaper for testing), but I messed up soldering on the main CPLD and had to remove and replace it.
The new CPLD checked out and the board worked well without AltRAM enabled (different memory configuration so I started off without it).
As I brought up the AltRAM the board ran for a some time (a few minutes) before failing with many CPLD pins now measuring a short to ground. The CPLD had got very hot before its failure, the original runs cool a second £20 CPLD blown in the space of a day. Ouch.
I assumed I'd introduced a short somewhere so perhaps I shouldn't trust this board with a third CPLD rework.
So I built a third board, transferring all the components, bar the CPU socket and the CPLD from the old one. Soldered on yet another new CLPD, this time making sure it was absolutely perfectly aligned. Buzzed out as many lines as I could think to try, flashed the firmware. Worked first time. Brilliant.
- dfbr3_3_bang.jpeg (222.66 KiB) Viewed 2184 times
Except whilst I was sat there watching a test run, all the lights went out.
It had done it again. The CPLD had died with a large number of its lines short. Again it had been running quite hot beforehand. Surely a sign of something being not quite right, but what?
Clearly nothing was directly shorted else it wouldn't work at all, but could there be a low resistance path between a couple of pins? Something I've not been able to meter out, but maybe have a low impedance at megahertz-level switching?
The difference between the working board and the original design is:-
- ENABLE pin (p5) not working on the original. Originally jumpered to 5V or GND. Re-routed to pin 3 and now either pulled high by 10K or jumpered to ground;
- DQM0 pin (one of the SDRAM data masks), pin 4, track seems damaged after some rework around the crystal oscillator. Re-routed to pin 133;
- CPU clock out (pin 113) disabled and re-routed to pin 38 (a global clock pin) to experiment with different termination options;
- RAM clock out (pin 12) disabled and re-routed to pin 39, again for termination experiments;
So shall I gamble my last CPLD on this, cleaned up board?
- dfbr3_3_cpldkiller.JPG (208.98 KiB) Viewed 2184 times
I'm tempted to give it one more go, perhaps replicating the bodges from board 1 and, if that works, undoing them one at a time to see if I can identify the problem to feed back into rev 4. Better I learn something now than when rev4 has the same problem?
I dunno. What do you we think? Worthwhile? Give it up as a bad job? Perhaps someone can see an obvious mistake? Should I pile more capacitance on the CPLD (three 100nF one 1uF)? I'm deeply suspicious of that ENABLE line myself, but without much to back it up.
The CPLD-killer is haunting me!
BW
