DFB1r4 design discussion thread

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Re: DFB1r4 design discussion thread

Post by exxos » Sun Nov 21, 2021 6:43 pm

Leave no stone unturned as they say :) working or not, I think no experiment is a waste of time, it's all information we didn't have before :)
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Re: DFB1r4 design discussion thread

Post by Badwolf » Tue Nov 23, 2021 11:08 am

Right, I've observed an odd phenomenon which I could do with a bit of advice on from people who Know What They're Doing (TM).

I'm still chasing the elusive reliable DSP access. I observed that accessing the DSP was more relaible when I was probing the motherboard's address strobe (XAS) line than when I wasn't.

So, since slapping pull-ups on everything has been my weekend's enterprise, I put a pull-up on it.

Things got better, but weren't quite perfect, so I varied the resistance. Dropping it to 5k or under seemed to have a negative effect, so I went higher.

150k seemed to work surprsingly well. But what effect was it having? So I had an idea -- perhaps it wasn't the pull-up effect at all but the capacitance effect of the fly-lead? Sure enough, 1 megaohm seemed to work as well as anything. So did plugging in the one megaohm fly lead, but not actually attaching the other end.

So it looks like a bit of capacitance on the XAS line improves DSP readability.

It therefore have a couple of questions for those with experience of such voodoo:

1) What could be the mechanism going on here, do you think? Softer edges? Delayed deactivation? How would that make things better?
2) Is this remotely normal? Is intentionally loading capacitance onto a motherboard line a good idea?

I've not tried actually soldering a cap onto the line yet. Should I? What would I go for if I did 10pF?

Ta,

A confused BW.
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Re: DFB1r4 design discussion thread

Post by exxos » Tue Nov 23, 2021 11:22 am

I've had those issues as well. I've had 33pf on DTACK as my TF536 wouldn't boot without it. On the STE I've had 33pf on the 8mhz clock as once the loading changes, it oscillates more .. I think with the PLDs being so fast, they can react to noise.

You would need to look at AS on your scope with x10 probe while accessing the DSP. Such problems can be difficult to diagnose. Part of the clock buffer patch sees around 2volt drop from end to end. So you can imagine what that does to logic levels.
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Re: DFB1r4 design discussion thread

Post by Badwolf » Tue Nov 23, 2021 11:37 am

exxos wrote:
Tue Nov 23, 2021 11:22 am
I've had those issues as well. I've had 33pf on DTACK as my TF536 wouldn't boot without it. On the STE I've had 33pf on the 8mhz clock as once the loading changes, it oscillates more .. I think with the PLDs being so fast, they can react to noise.

You would need to look at AS on your scope with x10 probe while accessing the DSP. Such problems can be difficult to diagnose. Part of the clock buffer patch sees around 2volt drop from end to end. So you can imagine what that does to logic levels.
In my case it's the CPLD driving XAS, rather than reacting to it.

I wondered if it might be stimulating a slight extra delay (slowing the rise [or fall] of the edge, for example), so did some experimenting with delaying XAS, or speeding up the UDS/LDS.

What I found with those was that UDS/LDS have to be asserted after XAS, but *only just* after. Any more than 20ns doesn't work and if they're completely simultaneous with XAS or 10ns before XAS, things don't work either. This seems odd to me, but when you consider A0 is derived from UDS/LDS and it really ought to be stable when XAS is asserted, having them as close as possible to each other kind of makes sense.

Anyway, changing the activation or deactivation points of XAS doesn't have any positive effect and the variations above just completed broke everything, so my initial theory about it being a delay stimulant might be bogus.

Will probe it and see if there's anything obvious, but otherwise if it's safe to do so I'll try whacking on some capacitance, then.

Cheers,

BW.
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Re: DFB1r4 design discussion thread

Post by exxos » Tue Nov 23, 2021 11:42 am

Connect your scope to a gnd near the DSP then look at AS on your board and take note of noise and low high logic levels / DC offsets etc.
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Re: DFB1r4 design discussion thread

Post by Badwolf » Tue Nov 23, 2021 1:42 pm

exxos wrote:
Tue Nov 23, 2021 11:42 am
Connect your scope to a gnd near the DSP then look at AS on your board and take note of noise and low high logic levels / DC offsets etc.
XAS doesn't go anywhere near the DSP. Its involvement directly stops at U68, just beneath the clock patch.

Image

But, sure, I'll do a before-and-after scope there. :)

BW
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Re: DFB1r4 design discussion thread

Post by Badwolf » Tue Nov 23, 2021 9:07 pm

Right. That AS line is so on the edge of working that even probing it at 10x causes the DSP to fail.

But I took some other snaps whilst I had all the gear out.

In the below the top trace is XAS the bottom trace is the DSP chip select, and trigger.

This is my 'normal' configuration. Board enabled, no flylead on AS. This doesn't work reliably.

nowork_no_cap.bmp.png
nowork_no_cap.bmp.png (7.6 KiB) Viewed 187 times

This is with the flylead. This is almost reliable, but doesn't work at all when probed:

nowork_flylead.bmp.png
nowork_flylead.bmp.png (7.59 KiB) Viewed 187 times

And, for reference, here's the stock Falcon (this does work when probed):

stock.bmp.png
stock.bmp.png (9.17 KiB) Viewed 187 times


Now, here's the stock but with XAS plotted with CLK using the DSP_CS line as an external trigger. This is solid timing-wise when viewed in realtime.

stock_v_clk.bmp.png
stock_v_clk.bmp.png (9.74 KiB) Viewed 187 times

Here's three different snapshots of my board with CLK:

nowork_v_clk.bmp.png
nowork_v_clk.bmp.png (9.63 KiB) Viewed 187 times
nowork_v_clk2.bmp.png
nowork_v_clk2.bmp.png (9.68 KiB) Viewed 187 times
nowork_v_clk_3.bmp.png
nowork_v_clk_3.bmp.png (9.63 KiB) Viewed 187 times

As you can see, timing varies considerably -- by up to one clock cycle -- and nothing comes close to the tight two-cycle timing of the stock Falcon.

So whilst putting a bit of capacitance may improve things, I think it's purely by chance as it somehow jiggers timings.


I now have even *less* idea what's going on. That variation of the falling edge against the clock has me completely confused.

BW
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Re: DFB1r4 design discussion thread

Post by exxos » Tue Nov 23, 2021 9:42 pm

It's hard to tell, but that low level ringing is like 1V ? I've had waves like that on clocks which screw up..

For shits and giggles, why not lift the DSP_CS and put something like 100R from the GAL to CS line to see if it limits the ringing and see if it helps or not ?
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Re: DFB1r4 design discussion thread

Post by Badwolf » Tue Nov 23, 2021 10:34 pm

exxos wrote:
Tue Nov 23, 2021 9:42 pm
Its hard to tell, but that low level ringing is like 1V ? I've had waves like that on clocks which screw up..
Ah, sorry -- the grounding point on the DSP_CS trace is suboptimal (I ran out of chip clips and I was only really using it as a trigger).

I doubt the ringing is anywhere near that bad IRL -- the CS trace is almost identical on the stock version.
For shits and giggles, why not lift the DSP_CS and put something like 100R from the GAL to CS line to see if it limits the ringing and see if it helps or not ?
I'm building up an adapter for that GAL so I can intercept and do things with that line, though. I'll certainly give that a go. Ta.

In the meantime I re-introduced a clock dependency to my assertion of AS. That's taken RAM access from 100% down to 91%, but when I saw how bad that jitter was I thought I'd better try something. It hasn't had much effect, but I feel more comfortable with it whilst testing.

What I did notice, though, is that in the stock mode the AS line is pulled up to 5V after the initial high-drive whereas mine holds steady at 3V3. I wonder if going high-Z one cycle after driving AS high might have any effect?

I also scoped out UDS and LDS. These seem almost identical to a read on the stock version, so that's fine. A write on stock goes low one clock cycle later, but that's not comparable to my use case as I need UDS/LDS to generate A0, which the stock CPU doesn't have to do (they're working 'in reverse' for me).

I'm tempted to start appealing for CT2 or CT60 users to scope their XAS, UDS, LDS and DSP_CS pins for me!

BW
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Re: DFB1r4 design discussion thread

Post by exxos » Tue Nov 23, 2021 10:50 pm

Badwolf wrote:
Tue Nov 23, 2021 10:34 pm
What I did notice, though, is that in the stock mode the AS line is pulled up to 5V after the initial high-drive whereas mine holds steady at 3V3. I wonder if going high-Z one cycle after driving AS high might have any effect?
Not sure why it's at 3.3V unless you're driving it high from the PLD ? It should never be driven high anyway. Only 0V and Z. So something doesn't sound right there as it should be 0V and 5V (or nearas) even when being driven from those PLDs ?
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