exxos wrote: ↑
Thu Nov 25, 2021 12:12 am
OK, so why doesn't the stock machine suffer the same fate ?
As I understand it, the address (and data) lines are still driven after AS and DS are negated until the next rising edge of the clock. That must be, on the stock system, enough time for the DSP to latch, else Atari could not have got away with their GAL implementation of DSP_CS.
So my system happily carries on asserting A1-23 and D16-31, but A0 is asserted by the GALs, which just pass through /UDS as A0. So when UDS goes high, a smidge later A0 starts falling *in parallel with* DSP_CS rising.
It's a race. If DSP_CS rises fast enough, it'll work. If A0 drops slightly faster, it'll only work on even numbers.
I could probably influence the timings slightly with my random extra bits of capacitance here and there. Even attaching an oscilloscope to the AS line was enough to knock it off kilter.
It also explains why I could read but not write. When I read, the CPU latches the data on the next falling clock edge after DSACK0 is seen. All the lines are stil properly asserted. I couldn't write
, however, as writes to the DSP are only actioned when FFA207 is written to. An odd
address! Remember high UDS = low A0 => even addresses only!
I've had my confidence in a tentative solution knocked back so many times that I'm touching wood left right and centre here, but so far this is all consistent.
I think I could probably even wind my extended assertion of UDS & LDS back half a clock to match the 030's assert-until-next-rising-edge behaviour.