DFB1r4 design discussion thread

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Icky
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Re: DFB1r4 design discussion thread

Post by Icky » Wed Sep 15, 2021 1:44 pm

Badwolf wrote:
Wed Sep 15, 2021 10:07 am
Spent most of last evening trying to sort out insurance for my lad who's just passed his driving test. Not fun.
I don't envy you @Badwolf when my daughter passed her test the first years insurance was astronomical.
Badwolf wrote:
Wed Sep 15, 2021 10:07 am
So now it's bricked. Bah.
Always a PITA when that happens. Have had many a board in that state. I feel your pain as it adds extra time to build another board.

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Re: DFB1r4 design discussion thread

Post by Badwolf » Wed Sep 15, 2021 4:42 pm

Icky wrote:
Wed Sep 15, 2021 1:44 pm
Badwolf wrote:
Wed Sep 15, 2021 10:07 am
So now it's bricked. Bah.
Always a PITA when that happens. Have had many a board in that state. I feel your pain as it adds extra time to build another board.
Thanks, mate.

Do you know if a working version if Impact can actually resurrect them, or is it not worth me even trying?

Cheers,

BW.
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Re: DFB1r4 design discussion thread

Post by Badwolf » Thu Sep 16, 2021 2:58 pm

Status update:

Built up a new minimal board: headers, CPLD, voltage regulator, associated caps.

Doing a ROM decode (after I figured out it wouldn't work testing lines A[31:16] given only lines A[23:1] exist!) seems to work properly, so it looks like the address lines are good.

I hacked a very quick AS assertion test but that *also* seemed to fail. I admit I didn't have a lot of time so this might not have been done perfectly, but if this is reproducible it does point to architecture rather than a soldering or firmware error.

Balls. I'll need to get the schematics out between versions and see what could have possibly changed. *If* it's reproducible. :(

BW
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Re: DFB1r4 design discussion thread

Post by exxos » Thu Sep 16, 2021 3:11 pm

Badwolf wrote:
Thu Sep 16, 2021 2:58 pm
I hacked a very quick AS assertion test but that *also* seemed to fail.
Doing what exactly ?
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Re: DFB1r4 design discussion thread

Post by Badwolf » Thu Sep 16, 2021 3:59 pm

exxos wrote:
Thu Sep 16, 2021 3:11 pm
Badwolf wrote:
Thu Sep 16, 2021 2:58 pm
I hacked a very quick AS assertion test but that *also* seemed to fail.
Doing what exactly ?
* Stock Bus Arb to gain bus mastery.

* 9 bit counter on xcpuclk held at 0 when RST low.

* Assert A=31'h0 when I'm bus master, 31'hz otherwise.

* Assert AS, UDS and LDS when 1) I'm bus master and 2) when certain bits are set (off the top of my head something like counter[7] == 1'b1 -- so that it's asserted for 128 clock cycles every 512, for example -- enough time to see the bus error).

* Monitor AS, XDTACK, BERR, XBGK and BMODE (the latter two good indicators of bus mastery being negotiated properly).

But I was very rushed with this last night so didn't rig up a the logic analyser, just probed one at a time. That's next so I can record them all in parallel.

BW
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Re: DFB1r4 design discussion thread

Post by exxos » Thu Sep 16, 2021 4:14 pm

Badwolf wrote:
Thu Sep 16, 2021 3:59 pm
* 9 bit counter on xcpuclk held at 0 when RST low.
Not clocking the CPU while in reset ? if so, It should not really be done as CPU has to clear out internal registers during reset. I do not remember exactly, but it is like 100 clocks minimum or something like that.
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Re: DFB1r4 design discussion thread

Post by Badwolf » Thu Sep 16, 2021 4:22 pm

exxos wrote:
Thu Sep 16, 2021 4:14 pm
Badwolf wrote:
Thu Sep 16, 2021 3:59 pm
* 9 bit counter on xcpuclk held at 0 when RST low.
Not clocking the CPU while in reset ? if so, It should not really be done as CPU has to clear out internal registers during reset. I do not remember exactly, but it is like 100 clocks minimum or something like that.
Ah no, my counter increments on XCPUCLK (the 8MHz motherboard clock), not the other way around. I just don't run the counter when in reset. Not needed really as nothing happens until bus arb is complete anyway.

The counter's just there so it'll try an AS for 128 clocks every 512 clocks -- means I can scope it easily.

I don't have an external CPU in place, this is just a CPLD hanging off the expansion port at the moment.

BW
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Re: DFB1r4 design discussion thread

Post by Badwolf » Thu Sep 16, 2021 8:57 pm

Here are the traces in this CPU-less bus-arb-plus-read configuration:

Screenshot 2021-09-16 at 20.54.03.png
Screenshot 2021-09-16 at 20.54.03.png (58.74 KiB) Viewed 96 times

I can't see anything obviously wrong here, but no DTACK and instead Bus Error right on cue. :(

This is requesting a word read from 0x000000. Going to try some more tricks.

BW
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Re: DFB1r4 design discussion thread

Post by Badwolf » Thu Sep 16, 2021 8:59 pm

Oooooooooooooooh, poop.

</nasty pang of foreboding inspiration>
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Re: DFB1r4 design discussion thread

Post by Badwolf » Thu Sep 16, 2021 9:11 pm

Badwolf wrote:
Thu Sep 16, 2021 8:59 pm
Oooooooooooooooh, poop.

</nasty pang of foreboding inspiration>
Actually, it doesn't look that that was it. I sort of wish it were now. I suddenly though that perhaps COMBEL samples the FC[2:0] lines in determining whether to throw a BERR or not, and I wasn't setting them. Worse than that, they're unconnected on this board whereas they were straight-throughs on the old one -- so at last a theory about a board difference.

I frigged a quick test, but it didn't seem to have any effect, so maybe not, but I think I apply some bodge wires anyway, on the off-chance.

BW
Falcdate Use the internet to work around dead Falcon NVRAM battery
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