exxos wrote: ↑
Sat Jan 15, 2022 1:26 am
It gets tricky to work out as there is PLD delays in the mix. If we went for 64mhz cpu, say 15ns, assume 2 clocks for the bus cycle, 30ns, assume 10ns for the PLD.. The ram would have to be ready in 20ns to keep up.
SDR SDRAM needs *4* clocks (minimum) for each random access from AS to data. It then needs another three cycles ‘recovery’, if you like (precharge). No problem, you might think, just run at twice, or more times, the CPU clock. Which is perfectly normal, but then you run into minimum times between commands, and have to pad out the access anyway.
I’d have to go through the data sheet and work out the optimum frequency that gives the lowest response time. My guess is we end up at around 60-70ns effective for our use case.
(Once you’ve opened a column, you can whizz down the data at one word every 7.5ns, but that is of absolutely no use to us, I’m afraid)
So how are you working out 50MHz access speeds then ? I assume you don't have wait states in there ?
But if TFs controller is faster, then use that ? He did say a while back I could use it, just never have time to build a board up like you have done. I think I had it up to 66mhz speeds at one point. But CPU and RAM brands are likely factors there also.
Once the CPU freq is beyond about 25MHz there are wait states on read accesses (but not writes). This is why you see memspeed figures in the 20s and 30s MB/s for read on my and Stephen’s cards, but writes are at the theoretical 40ish MB/s for a 50MHz processor.
My current controller is a hybrid of my own design from DFB1r3 and Stephen’s from TF330. I’ve basically credited Stephen as the author of it in the source.
My board was probably not really up to clocking the CPLD at 100 so I had a lot of trouble trying to do the double clocked routine. I rewrote it for 50 for ease of development (it also helps simplify my clock switching, which is hard on the Falcon) as the effective throughput cost is relatively low.
The speed boost should still be considerable, but it won’t be on a par with SRAM.
I’m planning to do development with a 32MHz oscillator at first, then will think about a 66 or similar. 100 is the limit of the CPLD.