[Video] A simple 16MHz hack for my STE: why memory access is so important.

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exxos
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Re: [Video] A simple 16MHz hack for my STE: why memory access is so important.

Post by exxos » Fri Jan 14, 2022 8:45 pm

Badwolf wrote:
Fri Jan 14, 2022 8:25 pm
I'm hoping to get SDRAM working and send one to Exxos to have a play with. He may be able to drop in his accelerator equations, for example.
....
This initial version won't be so cheap. The SDRAM was out of stock so I'll be putting a 16MB one on there and the CPLD I'm using is intentionally the biggest that'll fit the footprint to aid development.
16MB might work out good for other usage actually. With flashy clock I intended to copy ROM into SRAM because the ROM speed maxes out at 55ns. I really need something in the order of 10ns ROM. But the only thing that fast was SRAM at 10ns speeds. I hit a bit of a brick wall because my PLD simply ran out of space to fit all the logic in :(

As you undoubtedly know, normally this is what the 030 MMU does/can do, to remap ROM into RAM. But this is not so simple with a 68000. So what was on the cards was flashy clock would copy ROM into RAM at power up. Basically it would need a huge binary counter to step through the addresses. Later I thought of just cheating and copying the ROM with the CPU after power up. Because then a register can be flipped to SRAM when the copy has been done. So any ROM addresses will actually be read from a dedicated SRAM.

While there are programs which allegedly can copy ROM into alt-ram anyway, I have never got these to function properly and just see it as a total PITA thing to do anyway. I also think TOS is not happy running from alt-ram, which I ran into with the TF536.

So just copying the ROM to a new fast small SRAM was the plan. Then there is no software intervention or anything else required. As far as the system is concerned ROM is still in ROM space, just running from SRAM at much higher speeds. TOS Will still running the expected address ranges. Everything should be overall happier!

8MB not technically the limit anyway. I think you could go up to 10MB or even 12MB.. But people moaned about that because of graphics cards and other stuff in the address range. But if this was switchable anyway..

Badwolf wrote:
Fri Jan 14, 2022 8:25 pm
Aye. Although, Darklord, co-operation in general is a bit awkward as basically I'm a hobbiest giving away the designs and not making them. I can't really sidle up to Christian or Matthias and say, "Hey, boys. Let's get these two talking" until I actually have a working design. Even then, mine's likely to be evolved and changed by people -- it's not really a product. If those guys are selling and supporting theirs, they don't want that unknown interfering with things.
Indeed this is why I cannot really open source or collaborate with anyone else on my projects. Imagine if I gave away tomorrow everything I have ever worked on, I might as well close shop because every man and his dog would be making it. It is also again the problem of open sourcing stuff as terrible fire and others have found out. Good in some respects but not in others. UBE made and sold his VGA adapters, He was selling them to me and I was selling them in my store, so he was getting something as well as myself. But he also open sourced it, then loads of other people basically cloned it. In a way UBE shot himself in the foot because you cannot really give something away and sell it the same time. Undoubtedly when you open source something everyone will rip it off with or without your permission anyway.
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Re: [Video] A simple 16MHz hack for my STE: why memory access is so important.

Post by czietz » Fri Jan 14, 2022 8:50 pm

Badwolf wrote:
Fri Jan 14, 2022 8:29 pm
Ah, so it's special RAM that's the key is it?
Yes, it is. Cache in its most simple form (direct-mapped cache) works as follows: Let's assume for the sake of the argument that you have 64 kiB of cache memory. Then, data from main memory address 0x000000 is cached at address 0x0000 in the cache; main memory address 0x002222 is at address 0x2222 in the cache, etc. But, main memory address 0x122222 would also be mapped to cache address 0x2222.

Hence, your cache has to remember which address it actually cached. This is called the "tag" and it is stored in the tag RAM. In the example above, the tag would be 0x00 or 0x12, the high bits of the address. The tag RAM is special because it not only very fast, but it also includes a built-in comparator. So you can ask the tag RAM the following question: Does cache address 0x2222 store data of main memory address 0x122222? This is done by comparing the tag to 0x12. The tag RAM provides a match / no match output.

For example, the Mach16 uses two IDT7174S tag RAMs. There are some on eBay for about 30 GBP, each.

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Re: [Video] A simple 16MHz hack for my STE: why memory access is so important.

Post by exxos » Fri Jan 14, 2022 9:17 pm

@agranlund went one better not long ago viewtopic.php?f=76&t=3682 It is something I wondered about for a long time, but did not really look into it because of the mentioned problems. Even so, with the H5 in motion and a new FPGA chipset, all this hacky booster stuff will be obsolete soon anyway ;)
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Re: [Video] A simple 16MHz hack for my STE: why memory access is so important.

Post by JezC » Fri Jan 14, 2022 10:16 pm

exxos wrote:
Fri Jan 14, 2022 9:17 pm
@agranlund went one better not long ago viewtopic.php?f=76&t=3682 It is something I wondered about for a long time, but did not really look into it because of the mentioned problems. Even so, with the H5 in motion and a new FPGA chipset, all this hacky booster stuff will be obsolete soon anyway ;)
Not quite sure that 'soon' is the word I would have chosen here...given previous comments about the workload & limited number of developers!
Though I'd be delighted to be proven wrong & have the option to get one of these for Christmas 2022! :D

Note that I'm not knocking the fine work done by everyone here, just recognising the problems of the ongoing component supplies (especially with some memories and CPLDs/FPGAs) as well as the amount of work to go through to complete the FPGA designs for the custom chips and then design the faster memory/processor solutions to make full use of them.

I'll volunteer here to help out as/when I can!

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Re: [Video] A simple 16MHz hack for my STE: why memory access is so important.

Post by exxos » Fri Jan 14, 2022 10:33 pm

JezC wrote:
Fri Jan 14, 2022 10:16 pm
Not quite sure that 'soon' is the word I would have chosen here...given previous comments about the workload & limited number of developers!
Though I'd be delighted to be proven wrong & have the option to get one of these for Christmas 2022! :D

Note that I'm not knocking the fine work done by everyone here, just recognising the problems of the ongoing component supplies (especially with some memories and CPLDs/FPGAs) as well as the amount of work to go through to complete the FPGA designs for the custom chips and then design the faster memory/processor solutions to make full use of them.
Yep part shortages have squatted a lot of projects. But I have been buying stuff as much as possible over the past year.. I am slowly catching up and when myself and @Icky Get back in full swing then things will rocket along again. Though I don't really want to hijack @Badwolfs Thread about all my ongoing projects :)
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Re: [Video] A simple 16MHz hack for my STE: why memory access is so important.

Post by Badwolf » Fri Jan 14, 2022 11:39 pm

exxos wrote:
Fri Jan 14, 2022 9:17 pm
@agranlund went one better not long ago viewtopic.php?f=76&t=3682 It is something I wondered about for a long time, but did not really look into it because of the mentioned problems. Even so, with the H5 in motion and a new FPGA chipset, all this hacky booster stuff will be obsolete soon anyway ;)
Oooo! I missed that thread. Cool. I had a project in mind that would sniff the screen address from Videl/MCU and mirror writes to it, but using hardware rather than software/MMU and to different ends, but all this stunt-memory business is extremely interesting. I did try to understand the 030's MMU once...

exxos wrote:
Fri Jan 14, 2022 8:45 pm
16MB might work out good for other usage actually. With flashy clock I intended to copy ROM into SRAM because the ROM speed maxes out at 55ns. I really need something in the order of 10ns ROM. But the only thing that fast was SRAM at 10ns speeds. I hit a bit of a brick wall because my PLD simply ran out of space to fit all the logic in :(
Crikey! 10ns is a big ask. This is the RAM I'm targeting: https://www.farnell.com/datasheets/2622019.pdf

I don't think it's going to be faster than the 55ns ROM. I'd have to properly work through the timings, but I think 70ns for random reads is the kind of territory these get into. It's a minimum of four clock cycles and once the clock gets up above around 50MHz mark we have to start worrying about minimum times between commands.

I think any CPU above ~25-30MHz is going to need wait states with anything affordable -- back to cache again? :twisted:

https://uk.farnell.com/integrated-silic ... dp/2901196

This doesn't look terrible for a ROM proxy, though. £2.60 each?

czietz wrote:
Fri Jan 14, 2022 8:50 pm
Yes, it is. Cache in its most simple form (direct-mapped cache) works as follows:

<snip>

The tag RAM is special because it not only very fast, but it also includes a built-in comparator. So you can ask the tag RAM the following question: Does cache address 0x2222 store data of main memory address 0x122222? This is done by comparing the tag to 0x12. The tag RAM provides a match / no match output.
Thanks for this excellent primer on a subject which, despite reading a few articles (ranging from layman to verilog-heavy), I've missed key concepts in.

I can't help wondering if a CPLD could hold these tags as registers?

The state machine might chew it up, though.

Anyway, I'm unlikely to find myself going down that road any time soon. All this STE stuff is just really me putting off pressing 'go' on the next £50 order of DFB1 boards.

I need to sanity check them one more time...

BW
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Re: [Video] A simple 16MHz hack for my STE: why memory access is so important.

Post by exxos » Fri Jan 14, 2022 11:48 pm

Badwolf wrote:
Fri Jan 14, 2022 11:39 pm
Crikey! 10ns is a big ask. This is the RAM I'm targeting: https://www.farnell.com/datasheets/2622019.pdf

I don't think it's going to be faster than the 55ns ROM. I'd have to properly work through the timings, but I think 70ns for random reads is the kind of territory these get into. It's a minimum of four clock cycles and once the clock gets up above around 50MHz mark we have to start worrying about minimum times between commands.
Must be doable though as the TFxxx series use 50Mhz CPU and SDRAM I think ?, not sure if that had waitstates, but that can keep up I think..
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Re: [Video] A simple 16MHz hack for my STE: why memory access is so important.

Post by Darklord » Fri Jan 14, 2022 11:51 pm

exxos wrote:
Fri Jan 14, 2022 7:02 pm
@Darklord It is indeed a good idea BUT, I tried to do that years ago with MonSTer's alt-ram like 10+ years ago ? it is what people wanted, but when I started investigating its operation with my boosters, well it just went the same way as many threads do on AF, In that I basically got shot down because my booster would not play with Monster. I was looking into it and offering possible solutions, but again.. Another reason why I left AF. Long story short, I really just gave up trying to work with other people just was not worth the effort. But as in general, people would rather complain and shoot down efforts rather than actually helping.

My STE booster has been on sale for a number of years now, if anyone really that bothered in a solution, it could have easily been done and I would have helped them make it compatible with the booster. But mostly these days I am concentrating on the H5 platform with the intention of just creating all the possible upgrades myself so I can make sure everything plays nicely together. We already have flash-rom, IDE, and many things in the prototyping stage. The only thing i've not had time to do , is work on a SDRAM controller. Pretty much everything else is done now.

But it seems at least @Badwolf Is looking to cooperate creating a alt-ram solution which will be compatible with boosters. With the H5 having multiple 68K sockets, my 64MHz SEC booster can be plugged in alongside such a alt-ram solution and I am sure myself and @Badwolf Can work out how to make them work nicely together. It really should not be that hard to do.
I understand. Chris, you do *TONS* of things for the Atari community, AF may not appreciate you and your efforts but we surely do!

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Re: [Video] A simple 16MHz hack for my STE: why memory access is so important.

Post by Darklord » Fri Jan 14, 2022 11:57 pm

Badwolf wrote:
Fri Jan 14, 2022 8:25 pm

Aye. Although, Darklord, co-operation in general is a bit awkward as basically I'm a hobbiest giving away the designs and not making them. I can't really sidle up to Christian or Matthias and say, "Hey, boys. Let's get these two talking" until I actually have a working design. Even then, mine's likely to be evolved and changed by people -- it's not really a product. If those guys are selling and supporting theirs, they don't want that unknown interfering with things.

This little board I've drawn up (it's still on its way -- I was planning to keep it under my hat a little while longer in case it just flat doesn't work) is meant to be primary an SDRAM dev board to meet Exxos' needs, but it should have enough smarts to also perform a bit of clock switching, do some ROM decoding, or whatever functionality I can jam into the CPLD.

I'm hoping to get SDRAM working and send one to Exxos to have a play with. He may be able to drop in his accelerator equations, for example.

If he likes it and it does a job. He'll be free to make and sell them. :-)

This initial version won't be so cheap. The SDRAM was out of stock so I'll be putting a 16MB one on there and the CPLD I'm using is intentionally the biggest that'll fit the footprint to aid development. But, when stocks finally get back to normal, an 8MB SDRAM chip will cost about £1.80. The CPLD I'm aiming for will be a fiver. The rest of the components are jellybean.

BW
Gotcha. Like I said, it was a random thought. Some cosmic particles not properly screened out by the Earth's atmosphere,
got caught in that poor head of mine and started rattling around... :lol:
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Re: [Video] A simple 16MHz hack for my STE: why memory access is so important.

Post by olivier.jan » Sat Jan 15, 2022 12:02 am

Would you consider going for FPGA instead of CPLD?
There are these nice (on paper) Chinese FPGA: GW1NR-9 from Gowin. It’s flash based so no need to have external memory to bootstrap the FPGA and it includes RAM directly with access time of 4.5ns.

The downsides are:
- no 5v but 3.3 is available
- onboard memory of 64Mb max (there is a 128Mb version, but it’s on 32bit bus)
- Packaging is tiny and most are BGA but some QFN are available.
- Difficult to source at the moment and prices are up in the 20-30€
- Maximum of 9k LUT

But it can easily replace the CPLD and provide RAM. In fact, it should even be possible to fit a 68k core inside..

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