exxos's Atari, Amiga & retro forum

I've just had a reply from Wolfgang saying that the chosen FPGA cannot run _slower_ than 16MHz*. While I don't understand how this mean the cores could've been tested in-situ during development, it definitely means that very few demos (and some games) will run correctly.

It's possible the VHDL could be run on other FPGAs which could run at cycle exact 8MHz as long as the code is good I guess. I will explore this with Wolfgang.

*) "the Cyclone2 does not support less than 16MHz frequency"

He said similar to me. He said the CPU runs at 16mhz and has a pseudo 8mhz mode, whatever that means.

So it seems the CPU has no fully compatible mode

I just got the benchmarks back from Wolfgang. Though I didn't mention to run in medium-res Results for mono won't compare to medium res even with a stock machine, so I have asked him to re-run the test in medium res.

From what I can tell so far, the system runs around 16MHz, or very close to, apart from the RAM access which is 100%. So I suspect the results to be very close to my V2.2 booster.. However, int-div on suska is 280%, not 185%, so assume the CPU runs in less cycles than the real CPU (maybe comparable to the 020).

Medium res benchmark..


Going by ROM its like a 16MHz machine. Other display tests look more like a 32MHz machine. Int-div looks somewhere around 25MHz machine.

So I think the Suska CPU is running instructions faster than a real 68000. Not saying this is good or bad, depends what the end result is desired.

By the looks of it, even granting its running 16MHz.. the results don't tally with a real 68000 benchmark. So emulating a real 8MHz 68000 I think isn't going to be possible. However, if we want the fastest 68000, then sure the suska would be ideal. Faster CPU always breaking things anyway, so no problem in that respect to use suska CPU.

With blitter enabled...


Below is 16MHz CPU, ROM, and blitter on.

.. and to put the CPU cycle accurate to rest..

Hi Chris,

i think, that my 68K00 CPU (and also the other ones) are not Cycle by
Cycle compatible. I have optimized a few things as you see for example
the very slow division of the MC68000.

Wolfgang

and if the core could run faster...

no, the implementation with the Cyclone limits it to 16MHz. But i am
currently working on a pipelined 68K10 which runs at about 55MHz.

I seem to remember running gembench but I used a real 68000 and sure I got around 99 or 100%. This was ages ago so maybe things have been updated, I took each core and wired them together as it is in the ST schematic s.

Stimpy wrote: ↑Mon Apr 16, 2018 11:02 am I seem to remember running gembench but I used a real 68000 and sure I got around 99 or 100%. This was ages ago so maybe things have been updated, I took each core and wired them together as it is in the ST schematic s.

It sounds like what I want to do, but I will start with blitter and throw everything at it before moving to anything else.

I'm asking Wolfgang about licenses.. I have no idea bout all that.. so want to make sure I have permission before I start..

I just purchased the Suska III

I think it will be useful for testing stuff out and ultimately making modifications as I will have a working platform to experiment with.. And probably screw it up totally


https://shop.inventronik.de/index.php?i ... &id_lang=2

I've talked to Wolfgang , and the has given me permission to use his code to create placement chipsets and even make changes

I suppose it would be possible to even add new features into the Blitter for example.. No idea what.. But the door is open least...

Cheers Chris for all the investment you're doing into our community